EDA_hg81
Advanced Member level 2
lookup table vhdl
I want to find an efficient way to build the compact lookup table inside FPGA based on following code:
Currently I detect all input 64 formats by using “if” and “elsif”, but this way is too timing consuming.
If I use ROM to build the lookup table, so much memory space is going to be wasted
Do you have any idea about how to build a much more efficient and compact look up table inside FPGA?
Very appreciate for you suggestions.
I want to find an efficient way to build the compact lookup table inside FPGA based on following code:
Currently I detect all input 64 formats by using “if” and “elsif”, but this way is too timing consuming.
If I use ROM to build the lookup table, so much memory space is going to be wasted
Do you have any idea about how to build a much more efficient and compact look up table inside FPGA?
Code:
Case state is
When idle =>
if ( trigger = '1' and formatdata( 31 downto 28) = x"6" and formatdata( 27 downto 16) = x"4D3" and x"06c8" >= formatdata( 15 downto 0 ) and formatdata( 15 downto 0 ) >= x"06C6")then
………………………………..
elsif ( trigger = '1' and formatdata( 31 downto 28) = x"6" and formatdata( 27 downto 16) = x"4D3" and x"06c8" >= formatdata( 15 downto 0 ) and formatdata( 15 downto 0 ) >= x"06C6")then
………………………………..
end if;
When output =>
……………………
When others =>
…………………...
End case;
Very appreciate for you suggestions.