matrixofdynamism
Advanced Member level 2
Functions and procedures are used to define often repeated sequence of instructions on data into a single place like in any other language. Is it true that in VHDL they are only able to infer combinatorial logic and never any registers? Is this true even if they are called from a process under rising_edge(clk) being true?
Is there no way for them to infer registers at all?
Is there no way for them to infer registers at all?