mburakbaran
Member level 2
Hello all,
I have designed a Class AB amplifier, schematic level simulations suggested a gain of 93dB, yet after parasitic RC extraction with Quantus PVS, post-layout simulations suggest 10dB less gain. Do you have any insight what might be the reason? There is no gain drop if the extraction is C only. Which may suggest it has something to the with a parasitic resistance deteriorating the performance. But I tried my best to come up with a decent layout. Used interdigitized current mirrors and input pair for better matching etc. After the simulation, I am checking the DC operating points, for some reason it only shows the unit transistors values (say, if a certain transistor is fingered 30 times, i can see the current, gm etc of one only). But if I multiply the value, the total gm, current etc seems like in good agreement with the simulations. So that leaves me thinking. Any ideas? Thanks in advance.
I have designed a Class AB amplifier, schematic level simulations suggested a gain of 93dB, yet after parasitic RC extraction with Quantus PVS, post-layout simulations suggest 10dB less gain. Do you have any insight what might be the reason? There is no gain drop if the extraction is C only. Which may suggest it has something to the with a parasitic resistance deteriorating the performance. But I tried my best to come up with a decent layout. Used interdigitized current mirrors and input pair for better matching etc. After the simulation, I am checking the DC operating points, for some reason it only shows the unit transistors values (say, if a certain transistor is fingered 30 times, i can see the current, gm etc of one only). But if I multiply the value, the total gm, current etc seems like in good agreement with the simulations. So that leaves me thinking. Any ideas? Thanks in advance.