pkoti83
Newbie level 5
In verilog design, we have ?: operator and if..else statement.
for ex: c = foo ? a:b
for ex: if (foo)
c = a;
else
c = b;
which one of the above code is preferable in verilog design prospective
- - - Updated - - -
and what is the difference between them.
Shall i use ?: operator in design rather than if..else . If Yes, why?
for ex: c = foo ? a:b
for ex: if (foo)
c = a;
else
c = b;
which one of the above code is preferable in verilog design prospective
- - - Updated - - -
and what is the difference between them.
Shall i use ?: operator in design rather than if..else . If Yes, why?