Help on PCB stack up for FPGA with uC design

Hi i am working on a FPGA with a uC design. The maximum frequency on the design will be a 50Mhz differential pair line. The board will have a Spartan-3AN connected to a Kinetis uC (Freescale Cortex-M4). The design will be implemented on a 4 layer board.

First of question is more generic, and not related to this project... despite the routing complexness.. when should i consider using a 4 layer board and not a dual layer one? I belive this is pretty much related to the maximum frequency and impedance control right?

Now related to this specific design. I have heared that when working with a 4 layer board i should consider to use the internal layers to power and GND and external layers for signal..

However on Kinetis documentation the two poissible layer stackup are the following:

4-Layer PCB A:
Layer 1 (top – MCU location)—Ground plane and pads for top mounted
components, no signals
Layer 2 (inner)—signals and power plane
Thick core
Layer 3 (inner)—signals and power plane
Layer 4 (bottom)—ground plane and pads for bottom mounted components, no
signals

4-Layer PCB B:
Layer 1 (top – MCU location)—signals and poured power
Layer 2 (inner)—ground plane
Thick core
Layer 3 (inner)—ground plane
Layer 4 (bottom)—signals and poured power

Where pouered power is a non contiguous power/gnd plane....

None of the both recommended stackup are the basic signal-gnd-vcc-signal

Can any one help me understand the good and bad points of each possible stack up possibility?

If i go to the basic stack up (signal on external layers and vcc and gnd on internal), which (vcc or gnd) should be underneath the top layer (where FPGA and uC are).

At the same situation, should i cover the unused parts of the external layers with GND or VCC? If yes which should i use? GND, VCC or both?

Finally, if happens that i can route my design on a 2 layer boards, what considerations should i take?

Thank you!

Both quoted stackups are rather special ones and hardly suitable for your design purposes, I presume. 4 Layer is almost mandatory for complex designs with high density packages and a larger amount of signals. You still would want to avoid packages like BGA for fully connected FPGAs, they rather demand for 6 layers.

A continuous GND plane should be considered in most cases. Because you'll most likely need a number of supply voltages (at least three), a splitted power plane could be reasonable for the other inner layer. Or mixed supply supply and signal wiring.

Sink0 said:

when should i consider using a 4 layer board and not a dual layer one? I belive this is pretty much related to the maximum frequency and impedance control right?

Click to expand...

Right. In 4-layer board you can made power and ground layers. This is very good for power integrity. Good power means stability also in high frequency operations. Also having gnd plane is better for impedance control because manufacturers need a reference plane to do impedance measurements in production.

Sink0 said:

Can any one help me understand the good and bad points of each possible stack up possibility?

Click to expand...

I think that such structures are recommended because they implement two ground references for signals.
In basic signal-vcc-gnd-signal structure there is only one ground reference and it is for bottom layer singnals. Top layer signals does not have ground reference. Impedance calculations are performed for either power or ground plane references, but in real life it is always better having ground below signals and diffpairs rather than power because is easier to calculate, easier to predict and easier to modify any signals with respect to ground, not power.
Also not good is power(ground) discontinuities. In this case you should carefully think about power integrity, and this is not so easy as in case with two large polygons.
Make vcc and gnd polygons as close as possible in stackup. You get a very large (in dimensions) capacitor. It will filter any high frequency noise bettet that any other cap you find on the market. Not use thick core between power and ground!
Finally, i recommend you using a classic stackup, until you exactly know what you are doing.

Thank you for your reply..

So i will for for classic stack up

So should i go for: TOP - GND - VCC - BOTTON

or TOP - VCC - GND - BOTTON

On top and botton, should i fill empty space with GND and VCC, if yes, which one is the best, or both (one each side).

I will have basically 3 power domains.. the input VCC, which is 16V, a 3V3 domain for Spartan VCCO and VCCAUX and Kinetis DVCC. And a 1.2V for Spartan VCCINT.

The AVCC and AGND of Kinetis will be filtered from DVCC and DGND, but there won't be any extra analog on this board, .. it will be placed on another board connected with pinheaders.... so i belive there is no need for a separeted amout of ground.

PS: Both (Spartan and Kinetis) are LQFP with 144 pins

Thank you!

Sink0 said:

So should i go for: TOP - GND - VCC - BOTTON

or TOP - VCC - GND - BOTTON

Click to expand...

Place all of your powers on one pwr layer to keep ground undisturbed. If you plan to place more parts on top then choose TOP-VCC-GND-BOTTOM. That is because you can't route good in top: components are on top. Route your signals mainly on bottom. Then you have good reference for bottom's impedance control and full empty layer without parts installed. In addition you will have power layer closer to components. Route ceramic caps in way PART_PIN-CAP_PIN-POWER_VIA. If you choose TOP-VCC-GND-BOTOM stackup then your power vias will connect to power layer through a smaller connect as you choose TOP-GND-PWR-BOT. You get then lower inductance in current path and higher capacitor performance in power filtering. And this is a key to good high spped design. Finally fill all empty space with GND.

Using the standard (classic) stack up, one of the signal layers will have the return currents running through the VCC layer, if you have splits in this layer it can cause problems for your high speed signals.
Look up planar capacitance, the planes have to be closely coupled (very thin dialectric) to get any appreciable capacitance.
I have done numerous Xilinx FPGA layouts but never on 4 layers, due to Signal Integrity, controlling SSN etc, here are a couple of relevant app notes, the top one being the most important.
https://www.xilinx.com/support/documentation/application_notes/xapp623.pdf
https://www.xilinx.com/support/documentation/white_papers/wp174.pdf

I have a different view on the power (other than GND) planes. Place the bypass capacitors near to the power supply pins (e.g. below a BGA package) and there are no return currents at all. Probably use local supply isles for Vcore or individual Vccio nodes. Continuous GND is a must, everything else is optional.

Hi FvM,
are you refering to the stack up or cap placement?
The Spartans usually have at least 3 voltages present and all grounds near the centre of the BGA, not good for simultaneous switching noise (re the ground pins on the newer Virtex 5 have been onptimes to reduce switching loops), so with one power layer, the signals in the next adjacent layer will couple to this power layer, and most probably signals will cross splits in this layer, causing a horrendus return path for the currents.Personaly for these sort of designs we never go below 8 layers, so that signals are next to a contigous ground and high speed signals can be run as stripline. If you run a microstrip signal layer next to a power layer the return current for that signal will be in the power layer. The decoupling capacitors will not affect this return current, as it is coupled to the signal track below the plane.
Ref Chapter 16.3... , Henry Ott , Electromagnetic Compatability Engineering. 16.3.2 covers split planes, both power and ground

I think, we are talking about different kinds of designs. I suggested a way to implement a 4 layer or possibly 6 layer PCB for basic requirements. It's feasible and can achieve acceptable signal quality and EMC behaviour. Continous supply voltage planes are neither an option in this case nor absolutely required.

What does worry me with a 4 layer design is avoiding signals coupling to the split power plane, I would in this instance go for sig-vcc-gnd-sig as suggested by Awaw and route all critical signals on the bottom layer such as the diff pair. Six still would give more flexability though. For 4 layers optimisation of the FPGA pin out will help ease the routing.

If the design has a relevant VCC, a VCC plane may be useful. Many FPGA designs haven't. The other point is, that your VCC plane will also receive unwanted return currents and "spill" them over the board if not tied to the GND plane by a mesh of decoupling capacitors. On the other hand, good decoupled supply isles or split planes can still act as shielding and signal return.

My suggestion is assuming, that top and bottom layer won't be sufficient for signals and the remaining supplies. If this is true, but you don't like the solution for the said reasons, you have to go for six layers.

Thank you for all this usefull information.

Spartan 3AN got just 2 power domains.. 3.3v and 1.2v, so i will be working with just 2 different power domains.. routing is pretty simple as i won't be using many pins of the Spartan 3AN.. and actually a 100 pin devices would be more than enough.. i am using a 3AN device due to the embedded flash. Actually the worst routing part is the FPGA J-TAG.. for some reason Xilinx place pins on oposite sides of the TQFP package.. i wonder why... The flexibility of FPGA makes all the remaining routing pretty simple. 6 layers is not an option now.. this is just a prof-of-concept prototype.. so do not got much budget for these boards...

A implementation question, at the present situation i am placing the decoupling capacitors on the botton layer to do not block pins connections (0402 package is a noway here as they will be handsoldered).. if i keep like this i belive more than half of my routing can be kept on the top layer, but i will still need a bit of routing on botton layer... I could place my capactiors on top layer, and route most of my signals on botton layer.. which one is more recommended?

And now a very specific question, and probably that is program dependent. I know i should not place a via to power planes between decoupling capacitor and power pins.. however, if i place the capacitors on the opposite layer.. i will have to use a via to connect top to botton layer, however, as the net is the same, it will eventually connect to the GND/VCC plane.. is there any know workaround to avoid this problem? I am designing the board at kikad (i know, but Altium is not an option right now).

Thank you!

Sink0 said:

I could place my capactiors on top layer, and route most of my signals on botton layer.. which one is more recommended?
...
is there any know workaround to avoid this problem?

Click to expand...

Again, as i said above, if you place parts including caps on top you get the best result including routing space. Placing caps on bottom is needed only in case of BGAs, where you can't connect a power pin with directly to cap pin. Such placement lead to greather inductance in current path. Here is two cases.
1. Cap on top. Routing looks like pin-etch-cap-via-plane. Here via to plane distance is small because plane is the second layer.
2. Cap on bottom. Routing looks like pin-etch-via(plane)-etch-cap. Here cap to plane distance is greather because plane is thid layer counting from bottom.
The more length the more inductance and this is bad.
Additionaly a cap is connected not directly to power pin but through via. This generally reduces performance. Again, BGAs is not case here.

As a more practical argument, I won't go for double-side assembly, if single side can achieve good performance.

I'm tempted to add a comment about the significance of via inductance and pin-via order, as addressed by awaw. You're right in principle. But compared to the huge inductance of TQFP and PQFP lead frames, the small additional amount is more or less negletable. If I see a routing advantage in placing a supply via on the inner side of a TQFP pin and the capacitor on the outer, I'll do without further considering. In addition, shortest path to the GND plane is highest priority for FPGA GND pins, second is short path to decoupling capacitor.

I can't follow the argument about 0402 package being to small for hand soldering, because the pins are still wider than 0.5 mm spaced TQFP pins.

Sinlge side assembly is impossible.. the board is 5x9 cm (although i would like to be 4X9 but it is ok).

It got 2 144 pins LQFP packages, 2 RJ45 jacks, 2 11x2 pinheader, spartan J-tag (2x7 2mm pitch), Kinetis J-Tag (5x2, 1.27mm pitch), 16 to 3.3v converter (MP2307 based), 1.2V linear, al decoupling capacitors, 2 M-LVDS transceivers (soic with 8 pins), DIP switch wtih 5 positions, pi-filter for AVCC and AGND, and some extra resistors and leds... impossible to fit in one side.. actually all power conversio is placed on botton already...

Actually i was considering place one of the big packages on botton.. but i will try to avoid that...

The problem with 0402 is not the distance between pads.. but the size of the componnet itself.. LQFP packages got a huge piece of plastic to hold with vacuum pen...

I would place the decoupling caps on the bottom side directly under the relevant power pins, as this is dead area and thus will save space then via out to the power plane. The picture below helps illustrate my point. A FvM points out, lead frame inductance is horrendus so the tiny extra bit added is immaterial, and using the plabes can be better than routes. There is a very good Xilinx data sheet on decoupling and the Virtex 5, that gives figures ro decoupling cap distance in relationship to the frequency and wvelength, and hwhat distance from a pin a decoupling cap can be and still be effective.

Thank you guys.. i will take all this in consideration...

Question about ground plane (and VCC plane), i have heared that i should not place anything (incluiding GND and VCC planes) under a crystal becouse that can chnagethe load capacitance resuling on a different frequency. However i have heared that is goo dto place a GND place under a crystal as it will shield it.. which one is right? On the Cystal layer all i am usgin is a guard ring..

Does this apply to active crystal oscilators?

Thank you!

The points mainly apply to low power watch crystals and not at all to crystal oscillator modules. The Oscin/out nets of regular MHz crystals should have GND plane below it as shield, if low jitter is an objective. The load capacitance can be corrected respectively.

How about on the same layer of the crystal? Should i clean the area around it, or can i fill with GND?

Thank you!

It isn't bad to keep interfering nets at a certain distance, or place a guard ring. For general purpose clocks without critical specification, it isn't necessary, I think.