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clock jitter and hold time

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dazzling_deepika

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jitter hold setup

I read some where that clock jitter does not effect hold time violation..is it true?if yes then why?
 

why jitter is not considered for hold

if jitter is delaying a clock (positive jitter) hold violation would be improved .. and probably jitter will always delay the clock so jitter will not effect hold violation ..

though i not 100% sure .. may be some back-end experts can comment on this ..
 

jitter hold time

Jitter is basically time variation of periodic signal.Jitter will not effect the hold requirement if the capture and launch flop clock is derived out of same same PLL.Basically they gets cancelled off..
 

clock does not hold time

Hold time is not dependent on frequency, so jitter effects normally do not lead to hold time violations
 

hold time launch flop

So if the jitter doesn't affect the hold time, it must affect the setup time, right?
 

clock hold

yes, jitter effects setup time as it can reduce the clock period. This can be modeled in your create_clock constraints by defining your period to include jitter
 

clock jitter hold time violation

BTW, jitter do affect hold time violation. Jitter is caused by the crosstalk on the clock nets (victim here). In that case, the clock net becomes either slower or faster based on the crosstalk. This impacts the hold timing.
 

Clock jitter effects the hold time, in general.

If the clock derives from the same clock source (PLL), then most of the jitter will cancel each other, but there is jitter brought in by clock tree buffers, and they are independent. So generally speaking, jitter still plays a role here in hold time.
 

Hi ebuddy,

I think when we have multicycle paths also hold will be effected by jitter..if incase we want to perform the hold check not on the same edge but at a later edge
 
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