Encounter RTL Compiler and Encounter test

jeannyguo said:

Now I meet some problems using Encounter RTL Compiler and Encounter test.
Specifically speaking,I need to generate some test vectors for ISCAS89 circuits,such as s298,s344 and so on.
I know that encounter test is a powerful ATPG tool,but it requires scanable circuits.I searched the Internet for ISCAS89 benchmark in verilog format,but unfornuately,it couldn't form a scan chain.
Encounter RTL compiler has a function to insert the scan chain and systhesis the circuit.
But I don't know how to use both software to achieve my goal.I wonder whether someone could be so kind to help me generate test vectors and send me the required input files and the general procedure.
Attached is the netlist of ISCAS89 s298 I found on Internet.
I really appreciate your help.

Click to expand...

gvk007 said:

please find a pdf file (attached with this message) for use with rtl compiler to synthesize a behavioural netlist (accu.v) along with scan insertion commands. Later the steps in the encounter test tools are also provided for generating atpg vectors. These atpg vectors are later applied to the gate level netlist to verify the stuck at 0/1 faults in the gate level netlist.

Gvk007

Click to expand...