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clock jitter in sigma delta ADC

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achilles09

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hello ,everyone. is it hard to implement a sample clock with 0.5ns jitter in SC sigma delta ADC?
 

I couldn't figure this out as well, but my work around was passing my clock throw a comparator build with mos, then including noise only in the comparator. I then measured the RMS jitter coming out of the comparator then increased the noise scale factor till I had a RMS jitter of 20pS which i needed for my sigma delta converter which I could then see the breaking down in my performance (thus it working!). Also just to note you are using a Switch cap sigma delta converter so it should be very immune to jitter! You only have the problem in CT sigma delta converters.
hope this helps
Jgk

Also if you figure out a better way of implementing the clock jitter please post it here. I would greatly appreciate it!
 
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