Any ideas about reducing design's setuptime?

Does anyone have any idea about how to reduce a vhdl pipelined design's setuptime. The design is implemented using xilinx tools.

We cannot do anything with design to change setup time.
Setup time depends on the Standard cell library the FPGA vendor used.
Correct me if I'm wrong

Really, but the set up time of the design clk??

do you mean reducing the setup time of your pipelined logic? there are many reasons that you might miss a setup time:

1.) too many levels of logic. This can be caused by bad coding style, or using complex operations.

2.) fixed location elements. Things like FIFO/RAMB/DSP48 or the GTP tiles, as well as ILOGIC/OLOGIC are fixed. When a path must start and end at one of these rare devices, it is much more likely to fail timing, as the placement might not be good.

3.) congestion. there are a limited number of high speed routes.

4.) impossible designs. while its true that you might get very creative with phase shifting the clock, or reducing the temperature range for the FPGA, some designs just can route from an element to the closest element and meet setup. Sometimes the constraints are not picked up correctly, and you end up with sub-ns requirements.


in the TWR file, #1 shows up when your timing score is based on a path that has many levels of logic. typically the logic/route percentage will show a higher level of logic. Logic optimizations such as retiming or manually optimizing your code will fix this.

#2 shows up more often with few levels of logic, and a long route. The special cases are when the CX/CY carry-chains are used frequenctly -- this implies the signal is being routed vertically. And when the logic starts/stops at rare elements.

FPGA_Editor can show these long paths and might help suggest why things didn't work. Prepare to be annoyed though -- very often the tools will place pipeline registers in the same slice, or fairly close, then route the remaining signal all the way across the chip.

Another issue is when area optimizations remove duplicate registers that would have allowed a copy of the signal to appear near the correct location on the chip.

#3 shows up when several seemingly easy paths also fail.

For #2/#3, you can look into using "smartXplorer" to run several MAP/PAR attempts. for Virtex4/5/6 devices, smartXplorer may be able to find a better placement for the rare elements. Really, try this first, as retiming has plenty of issues and I'm not convinced it always generates safe designs for the ISE implementation. Logic optimizations and manual fanout of logic can result in hard to read code, or can break already tested code.