bias circuit and differential buffer stage design

Can anyone offer me any hints on the design of differential buffer stage and bias circuit? I have read the "Low-jitter process-independend DLL and PLL based on self-biased techniques", but I still get confused about some issues. Actually, I am trying to design a DLL for which can generate phase delayed clock signal ( up to 200MHz) and varing duty cycles. I would like to have low jitter performance.
However, when I am simulating with the differential buffer delay stage, I found the differential output is not rail-to-rail, actually the control signal determines the ouput lowever level. If it is not rail-to-rail, how to connect to next delay cell? I will need at least 4 stages? And, since the input and output are differential signals, do I need to put any single-end to differential circuit before and after the delay cells?
Thank you very much. I attached the exact circuit I am using from that paper.

1, You are right, the output is not rail-to-rail. It doesn't matter.

2, use a diff to single stage after it. take a look at another paper of the same author

Thanks.
But what if I need several differential delay cells, the output is not rail-to-rail, will that affect the results?
And do you have any idea how to size the symmetric loads?
Thanks a lot.

Hi,
i am working on this delay cell for DLL design.
i just want to know how the symmetric load works.
and how a linear load have more dynamics power supply rejection.
if you have any good reference material, can you please share with me.

thanks