How to reduce PLL Noise due to buffer

Hi members,

The output of the VCO go to a buffer and then to the frequency divider. The buffer is non other than a chain of two inverters. When I simulate the PLL 60% of the noise come from this buffer.

How to resolve this problem ?

Thanks in advance for your replies.
Cheers,
Advares.

Getting a fast risetime out of a sinusoidal VCO is a problem,
you want a buffer that shares the source (VCO) ground
and supply and has a high first stage gain. Lower gain
against the leisurely risetime of the sine wave increases
the time spent in the linear region of the inverter, making
time noise out of voltage noise. A higher VCO output
amplitude and a low inverter input signal swing (ECL /
PECL perhaps?) might be better for jitter. If you have
to translate levels, do it after the signal has been squared
up and at a point where signal risetime is fast as possible.

Can you use a fast comparator? Try it first with a verilog/ahdl one.

First, what noise come from the buffer ? Device noise or 1/f or other?
Second , you can try according dick_freebird and erikl suggestion ,
third, I think you can use differential to sinle buffer such as comparator as the first buffer , remember , the VCO power supply and comparator power supply is different , former is analog or VCO power . another is digital .
Hope help you ...

dick_freebird said:

Getting a fast risetime out of a sinusoidal VCO is a problem,
you want a buffer that shares the source (VCO) ground
and supply and has a high first stage gain. Lower gain
against the leisurely risetime of the sine wave increases
the time spent in the linear region of the inverter, making
time noise out of voltage noise. A higher VCO output
amplitude and a low inverter input signal swing (ECL /
PECL perhaps?) might be better for jitter. If you have
to translate levels, do it after the signal has been squared
up and at a point where signal risetime is fast as possible.

Click to expand...

Thanks dick_freebird, Thanks ErikL, Thanks Bin_Wang.

Actually I was looking for a simple solution.
Does sizing buffer's transistor can resolve the problem or only the idea that you provide are solution ?

@dick_freebird
Good Idea Actually I use only mos transistor. I have no Bipolar transistor to use. Furthemore I prefer resistorless solutions If amplification is needed.
In my design I use only one power supply. Does using a double power supply can resolve the problem? Is it a garanteed ?

What about the Charge pump in this case Have It to share the power supply with the VCO or with the buffers ?


I'll try your solution dick_freebird and I'll be back.


@ErikL
Nice solution Erik. Unfortunatey I have no comparator in my library. As far as I know comparator are constructed with Amp op. The problem is that I've had never designed a Amp op before. I'll search for some proposed circuits (65 nm Amp op and Comparator) in recent IEEE paper and I'll try to implement them.

Could you please refert me to good materials ?

First, what noise come from the buffer ? Device noise or 1/f or other?
Second , you can try according dick_freebird and erikl suggestion ,
third, I think you can use differential to sinle buffer such as comparator as the first buffer , remember , the VCO power supply and comparator power supply is different , former is analog or VCO power . another is digital .
Hope help you ...

Click to expand...

It's 1/f noise.
I use a differential to single ended converter to convert the output of my differential VCO. Actually the second percentage of noise come from this converter and I'm thinking to eliminate it. What I dont understand is why have I to use two power supply when using a comparator. Doesn't the comparator solve the problem ?

Thanks again guys !
Cheers,
Advares.

You did the simulation, so the answer is at your fingertips, while we can only guess about the possible contribution of different noise sources.

However, you revealed part of puzzle in your second post. Of course a differential VCO's output has to be treated as any other high speed
differential signal, it has to be fed to a differential receiver. I would first think of circuits, that are commonly used for similar purposes as a
LVDS or Gigabit differential receiver. They are always single supply operated, I think.

The VCO buffer design is very critical to achieve good phase noise out of the PLL. If you try to use the blocks picked from the library, you'll have to settle for these numbers. Mostly in very high frequency VCO's the buffer consumes more current than the VCO itself. So the high noise numbers are nothing abnormal when working with a library low power comparator.
Design a dedicated differential to single ended converter with non-minimal lengths for the input pairs.
Make sure that the introduction of the d2s block does not affect the symmetry of the oscillator much.
Designing inverters with optimal stage efforts (e or 3 or 4) might not work here. In most cases, the stage effort is around 2 or even lesser is used to get lower phase noise.

Typically PLLs have 2 supplies to get lower phase noise, higher tuning range, etc. One for the low-frequency and analog part (PFD-CP, VCO) and the other for the high frequency part (Feedback and output dividers). So it is easy for anyone to assume that you are crossing two voltage domains in your comparator/buffer.

Cheers,
Saro