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charge pump PLL post simulation

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asdfjkl99

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post simulation

i designed a CPPLL with the SMIC 018um , the ouput of it is 480MHz. I used the ring oscillator for the VCO. When did the post-layout simulation of the VCO, i found the result of it is very different with the result of the pre-layout simulation. such as when the input of the VCO is 1.3v, the output frequency is 300M in post-sim while 500M in pre-sim. Is this OK?
 

charge pump pll

If you didn't estiamte/add the paracitical RC during pre-layout simulation,
of course you will got higher frequency than post-simulation.
 

pll charge pump simulation

Thank you for your reply. But the difference is too large. the delay time per delay cell of the VCO is changed from 2ns to 3.3ns.
 

simulation assurance

usually the Ring VCO tuning gain is very high, which means it is sensitive to any variations along the control line and GMcell gm change. Also, the layout parasitic definetly can cause 20% vco center frequency change.
 

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    asdfjkl99

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charge pump simulation

thank you for your help. But i found the Kvco also changed from 740 to 330, which cause the control voltage of the VCO change a lot. should i change the Kvco larger? Thank you.
 

simulation+charge pumping

hi,

you delay per cell is 2ns? you want 500MHz?


can you put your schematic here?
 

500M.....0.18.......difficult
 

Obviously your design should respect the post-simulation result.
First suggestion,you could present your schematic here.
Second,check your layout carefully and read the parasite parameter you extracted from the layout. Add the parasite capacitor to your schematic and simulate. You can evaluate the frequency shift then.

Third, 500M is not very difficult for 0.18um.
 

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