asdfjkl99
Newbie level 4
post simulation
i designed a CPPLL with the SMIC 018um , the ouput of it is 480MHz. I used the ring oscillator for the VCO. When did the post-layout simulation of the VCO, i found the result of it is very different with the result of the pre-layout simulation. such as when the input of the VCO is 1.3v, the output frequency is 300M in post-sim while 500M in pre-sim. Is this OK?
i designed a CPPLL with the SMIC 018um , the ouput of it is 480MHz. I used the ring oscillator for the VCO. When did the post-layout simulation of the VCO, i found the result of it is very different with the result of the pre-layout simulation. such as when the input of the VCO is 1.3v, the output frequency is 300M in post-sim while 500M in pre-sim. Is this OK?