Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

UGB Problem - variation is not reasonable for me

Status
Not open for further replies.
M

Monady

Advanced Member level 4
Joined
Dec 1, 2008
Messages
109
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,151
UGB Problem

Hi dear all friends
I used of folded cascade Unity-gain Buffer as depicted in the attached pic(open loop gain is greater than 800). I have an input voltage that varies between 250mV and 750mV. As you can see only around 450mV of input voltage, output able to track input. I need a buffer that be able to track input with offset below than 0.5mV and this variation that depicted in attached pic(that depends on input) is not reasonable for me.

I would be appreciated for any suggestion.
 

Re: UGB Problem

Hi,

Gain of 800 means, a systematic offset of 750m/800=0.9V at 750mV input. Thus, you have to increase the gain to make offset below 0.5V.

What is the value of vb1, vb2, vb4? What is Vt of M4 and M8?
 

    M

    Monady

    Points: 2
    Helpful Answer Positive Rating
UGB Problem

Dear Raviprasad_K, Thx for your reply,
when Vin=750mV, The output voltage=735mV, and it is so large offset!
i think your mean was 0.9mV offset, no 0.9V. if we use of this relation that you wrote, larger input results in lower offset, but if Vin=400mV then offset approximately is zero.i can't get it and mixed up.
vb1=1.06V, vb2=0.76V, Vb3=1.0V, Vb4=0.7V.
for Vin=750mV: Vth(M4)=5.707e-01 & Vth(M8 )=-5.105e-01
 

Re: UGB Problem

Oops! It is 0.9mV.

if we use of this relation that you wrote, larger input results in lower offset
Click to expand...
As voltage increases offset should increase. It is Vo/gain. Bias margins looks good enough.

What is the input voltage with which you have checked the gain? Did you check the gain with 250mV input and 750mV input? Are they above 800 in either case?
 

UGB Problem

i think i can't apply 250mV(differentially) to input because with gain=800, output must be 200V! thus i applied:
"Vin+=dc 0.5 ac 1" & "Vin-=dc 0.5 ac 0" and then i read gain from .Lis file.
I have a question:what is important for buffer designing except gain, for example in this case: 250mV<Vin<750mV and fin=500MHz,
which spec should take into consideration?
 

Re: UGB Problem

"Vin+=dc 0.5 ac 1" & "Vin-=dc 0.5 ac 0" and then i read gain from .Lis file.
Click to expand...

Apply Vin+=dc 0.25 ac 1 and Vin-=dc 0.25 ac 0 and then measure gain. Repeat the same for 0.75V.

Important spec to be considered are output load to be driven, slew rate.
 

Re: UGB Problem

In addition to the offset due to finite gain, you are observing the effect of common mode voltage on offset. Systematic offset is present as the output voltage is not the same at the voltage at the drain of M7(which must be around 470mV).
Any follower will have this offset, only the inverting amp is free from it.
 

    M

    Monady

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top