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Not necessarily,
But how to validate it? I mean the design.
Just write the code may not fulfill the needs in one shot.
Test bench will give the provision to test the capabilities, states etc.
So hope you understood the need for test bench.
You can compile/run your design directly using the simulator and stimulate the inputs from inside the simulator itself without a need to have a testbench .. yet, this can't be feasible in case of relatively big blocks with many I/Os
You can compile/run your design directly using the simulator and stimulate the inputs from inside the simulator itself without a need to have a testbench .. yet, this can't be feasible in case of relatively big blocks with many I/Os
Very well articulated indeed! This is what we cover in detail during our Comprehensive Functional Verification course. We explore several TB styles and go on to advanced, scalable testbenches using SystemVerilog. See: [url]https://sv-verif.blogspot.com/ [/url] for details.
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