walker5678
Full Member level 3
cmos opamp offset
If there is an CMOS opamp, whose input differencial pair is matched well, and also the internal circuits are well matched. Then how much will the offset voltage be for the real fab-out device? Is 10mV the normal level? And is it dependent much on the process capability?
Thanks.
If there is an CMOS opamp, whose input differencial pair is matched well, and also the internal circuits are well matched. Then how much will the offset voltage be for the real fab-out device? Is 10mV the normal level? And is it dependent much on the process capability?
Thanks.