Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

way for calculating lock time of a PLL in the design process

Status
Not open for further replies.

elec350

Full Member level 4
Joined
Dec 17, 2006
Messages
199
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Location
Iran
Activity points
2,548
PLL lock time [hlp]

hello
is there any way for calculating lock time of a PLL in the design process?
 

Re: PLL lock time [hlp]

As far as I know,the setting time can be affected by the gain of PFD
 

Re: PLL lock time [hlp]

Hi

I attach a simple papers vs example to calculate LPF and of course lock time, please review.

David
 

    elec350

    Points: 2
    Helpful Answer Positive Rating
Re: PLL lock time [hlp]

hello
what's about a hybrid PLL (using DDS)?
 

Re: PLL lock time [hlp]

The lock-time is easy to calculate:

With good accuracy it is simply: TL≈2*Pi/ωn
(ωn=loop natural frequency)

But realize that the lock-time is defined with the assumption that lock-in occurs within one beat-period. With other words: The frequency displacement is within the lock range.
 

Re: PLL lock time [hlp]

elec350 said:
hello
is there any way for calculating lock time of a PLL in the design process?

If you know the bandwidth of you loop filter,
For example 100KHz.
So the lock time will be close to 1/100K=10uS.
But the lock time will be affected by the initial dc level.
 

PLL lock time [hlp]

just some reference for you!
with LPF BW=100K,not too bad phase margin,Locktime can be reached 60us.

with LPF BW=200K,not too bad phase margin,Locktime can be reached 40us.
 

Re: PLL lock time [hlp]

iaman said:
just some reference for you!
with LPF BW=100K,not too bad phase margin,Locktime can be reached 60us.

with LPF BW=200K,not too bad phase margin,Locktime can be reached 40us.

Why?This is your experence?
But it is not match with the theory!
 

Re: PLL lock time [hlp]

frankiebai said:
iaman said:
just some reference for you!
with LPF BW=100K,not too bad phase margin,Locktime can be reached 60us.

with LPF BW=200K,not too bad phase margin,Locktime can be reached 40us.

Why?This is your experence?
But it is not match with the theory!

The lock-time can be calculated with the following :

Lock time≈K/ωn ,where K can be range from 3~6
(ωn=loop natural frequency)

the LPF BW=200K is the 3dB corner freq, the ωn can be got with BW3db/1.6.

the calculation is not very accurate, but I think it's a guide to optimize the design.
 

Re: PLL lock time [hlp]

In the mean time I have confirmed myself that the formula as given in my reply dated 21st of may 2008

lock-in time TL≈2*Pi/ωn

is recommended by several authors (Best, Gardner) for normal loop damping properties.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top