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What's the mininum PLL phase margin for the loop to work properly?

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gpwu

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What's the mininum PLL phase margin in order to for the loop work properly?
I designed one which is around 35 degree and it seems to work fine.
 

Re: PLL phase margin

I think 45 degree is needed, 60 degree is better.
Sometimes your simulation can not reflect the practical condition.
 

Re: PLL phase margin

i wanted to know on what basis u are saying 45 degree or 60 degree phase margin is required./....can u explain in detail
 

Re: PLL phase margin

basically you want the system to have a good dampling factor. 45-60 degree is a good number such that there is not much overshoot
 

PLL phase margin

for phase system you just need think 180 is enough
 

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    gpwu

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Re: PLL phase margin

PLL is 2 or more poles system, it has the damping problem.
 

PLL phase margin

stability and band width will be effected by the phase margine
also if you are using the passive filter than the value of the res and the cap will depand and hence the area of the chip.
damping factor also effect the settling time

hence think about the factors.
 

PLL phase margin

thank you guys for your help..this is a good forum.
Hope I'll post some better questions next time.
 

Re: PLL phase margin

35 is impossble, you have done a wrong calculation
 

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