need divide by 3 with 50% duty cycle circuit

divide by 3 circuit

hi all,
can any body send how to design divide by 3 with 50% duty cycle. Is there any general method to design odd dividers with 50% duty cycle

divide by 3 clock

Hi
Ya surely general method is there for it ,
For making odd dividers with 50% duty :
First Design the circuit how much mod counter you want , then take two T flip flop 1 +ve edge triggered and 1 -ve edge triggered (assume initial state for both of them is 1) and apply "1" input to both F/F.
For +ve Edge triggered F/F enable it at : 0 .
For -ve Edge triggered F/F enable it at : [ (n(n-1))/2 ] +1 .

and give output of both FF to an Exor gate ... you will get desired output.

Regards

divide by 3 circuit with 50 duty cycle

Clock Dividers Made Easy
Mohit Arora..
a gud papers in which ull find alll the speciality of clock division.

Added after 15 minutes:

this paper is there in this forum itself search and have it.

divide by three counter

uditkumar1983 said:

Hi
Ya surely general method is there for it ,
For making odd dividers with 50% duty :
First Design the circuit how much mod counter you want , then take two T flip flop 1 +ve edge triggered and 1 -ve edge triggered (assume initial state for both of them is 1) and apply "1" input to both F/F.
For +ve Edge triggered F/F enable it at : 0 .
For -ve Edge triggered F/F enable it at : [ (n(n-1))/2 ] +1 .

and give output of both FF to an Exor gate ... you will get desired output.

Regards

Click to expand...

The solution seems to be a tricky one.
May you explain what N is considered to???
What do you mean by ENABLED AT??? so you mean initialed with 0 or 1???

clock divide by 3

This note can help you:

"Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks"

h**p://www.onsemi.com/pub/Collateral/AND8001-D.PDF

Regards

divide by three circuit

srihari_adem said:

hi all,
can any body send how to design divide by 3 with 50% duty cycle. Is there any general method to design odd dividers with 50% duty cycle

Click to expand...

SNUG PAPER, CLOCK MADE EASY.


quan228228

Added after 7 minutes:

i cant upload the file. Pls email me, if you want it.

quan228228@hotmail.com


quan228228

divide by 3 with 50 duty cycle

[/quote]

The solution seems to be a tricky one.
May you explain what N is considered to???
What do you mean by ENABLED AT??? so you mean initialed with 0 or 1???[/quote]

Hi .
N => Mod of ur Counter
ex. For divide by 3 take N=3.

Enabled means Enabling of F/F .

so you mean initialed with 0 or 1??? =>ya initialied with '1'...

Any other comment ????

Regards

divide by 3 counter


The solution seems to be a tricky one.
May you explain what N is considered to???
What do you mean by ENABLED AT??? so you mean initialed with 0 or 1???[/quote]

Hi .
N => Mod of ur Counter
ex. For divide by 3 take N=3.

Enabled means Enabling of F/F .

so you mean initialed with 0 or 1??? =>ya initialied with '1'...

Any other comment ????

Regards[/quote]


Thanx for the response but I still not satisfied with your explanations.
If I will substitute N=3 then the result as your equation is: 4
So what I can do with this value when you ask to enabled at 4!!!
It still not clear to me.

Please, Please, Please explain more.
It will be great if may discussed an example.

divide by 3 clock circuit

you have to use double edge of the clock if you want it implemented in syncronous design.

divide by 3 counter design

khaila said:

The solution seems to be a tricky one.
May you explain what N is considered to???
What do you mean by ENABLED AT??? so you mean initialed with 0 or 1???

Click to expand...

Hi .
N => Mod of ur Counter
ex. For divide by 3 take N=3.

Enabled means Enabling of F/F .

so you mean initialed with 0 or 1??? =>ya initialied with '1'...

Any other comment ????

Regards[/quote]


Thanx for the response but I still not satisfied with your explanations.
If I will substitute N=3 then the result as your equation is: 4
So what I can do with this value when you ask to enabled at 4!!!
It still not clear to me.

Please, Please, Please explain more.
It will be great if may discussed an example.[/quote]

Hi
Sorry For my mistake it is [(n-1)/2]+1.

take Exp. for divide by 3 with 50 % duty cycle ..
so make circuit for Mod 3 counter (synchronous)...
so state of this counter is 0 ,1 & 2.
so now +ve edge F/F enabled it at 0
-ve edge triggered F/F enabled it at [(3-1)/2]+1 = 2
so now take o/p of both FF and give to input of exor gate ...
at o/p of exor gate you will get "Divide by3 with 50% duty cycle "..

Regards

Added after 1 minutes:

Hi
any other comments ?? Welcome..

Regards

divide by 3 counter circuit

Hi,

Please check out this old post.



Enjoy!

Hope it helps
-no_mad

divide by 3 50% duty cycle

uditkumar1983 said:

khaila said:

The solution seems to be a tricky one.
May you explain what N is considered to???
What do you mean by ENABLED AT??? so you mean initialed with 0 or 1???

Click to expand...

Hi .
N => Mod of ur Counter
ex. For divide by 3 take N=3.

Enabled means Enabling of F/F .

so you mean initialed with 0 or 1??? =>ya initialied with '1'...

Any other comment ????

Regards

Click to expand...

Thanx for the response but I still not satisfied with your explanations.
If I will substitute N=3 then the result as your equation is: 4
So what I can do with this value when you ask to enabled at 4!!!
It still not clear to me.

Please, Please, Please explain more.
It will be great if may discussed an example.[/quote]

Hi
Sorry For my mistake it is [(n-1)/2]+1.

take Exp. for divide by 3 with 50 % duty cycle ..
so make circuit for Mod 3 counter (synchronous)...
so state of this counter is 0 ,1 & 2.
so now +ve edge F/F enabled it at 0
-ve edge triggered F/F enabled it at [(3-1)/2]+1 = 2
so now take o/p of both FF and give to input of exor gate ...
at o/p of exor gate you will get "Divide by3 with 50% duty cycle "..

Regards

Added after 1 minutes:

Hi
any other comments ?? Welcome..

Regards[/quote]

Coooooooooooooooooooooooooooooooooooooooooooooooooooooooooooool
Thanx very much!!!