Problems with clock synthesization in VHDL

Re: clock synthesization

please i need your help ASAP

Re: clock synthesization

OK, Let me see if i understand this. You say that your clock not syntethize in VHDL...

In VHDL Behavioral code of your implementation (IP Core) you only can check rising edge or falling edge.

IF RISING_EDGE(Clk) THEN
... do something
END IF;

In VHDL Behavioral code of your test bench (waveforms file) you can define the clock duration.

PROCESS
BEGIN
Clk <= '1';
WAIT FOR 100 ns;
Clk <= '0';
WAIT FOR 100 ns;
END PROCESS;

I hope this help.

Re: clock synthesization

hi noha,

there should be no problem regarding your design clock
since clock is already an input
which will take its value from an oscillator on your kit

maybe you didn't write it completely right
you can either have it with wait statements or with rising_edge or falling_edge
or by clk'event and clk='1' (as rising_edge) or clk'event and clk='0' (as falling_edge)

Re: clock synthesization

thanks alot for your replies
but actually i have tried what you have both said
i wanna to change the current state of my state machine to athe next state when bup changes (either falling or rising) when i wrote that:

if (bup'event) then
state<= next_state

in synthisizing using xilinix it give me that error:
"unsupported clock"

i really donn know what to do

thanks in advance

Re: clock synthesization

hi Noha,

can u send me ur code plz and tell me what do u want to do exactly???

Regards,
Salma

Re: clock synthesization

Before answering u , i want to suggest you one thing. Whenever you are writing the code make sure that what hardware you are expecting for your code from the synthesis tool .

You said you want to change the state on both edges of the clock (I wonder ??) and ur code is

if (bup'event) then
state<= next_state

I think the above statement will never generate a flipflop (if synthesizable ??)instead it may generate a combinational circuit . You can't define a single flipflop which can output on both edges of the clock(I wonder if ?? and I want to see if any one provide ).

If you really want the output to be effected on both edges of the clock then use two seperate set of registers one operating with the pos edge of the clock and other with the neg edge of the same clock and assign the result of these two blocks concurrently to the final output.

I hope u got it ?? You try ur code as i said above and synthesize the code.
If I misunderstood ur problem plz let me know in detail about the same .

best regards,
subbu.

Re: clock synthesization

Hello!
It' illegal to write

if (bup'event) then
state<= next_state

because the synthesizing tool does'n know which type of flip-flop to implement.
It doesn't exist a flip-flop which work on the both fronts of the clock.

clock synthesization

only the rising edge can be used

Re: clock synthesization

i guess what was said about having two processes each for a specific task of changing the state upon rising or falling edges is most suitable, cause u can't have a synthesizable hardware which implements the state changes on both edges

or u can try to change your clock frequency (increase it) but that wouldn't be a good idea