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Problem with CRC VHDL code

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addn

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CRC Problem

hi,

for the following example CRC VHDL code


Code:
-----------------------------------------------------------------------
-- File:  PCK_CRC5_D8.vhd                              
-- Date:  Mon Oct  9 08:09:29 2006                                                      
--                                                                     
-- Copyright (C) 1999-2003 Easics NV.                 
-- This source file may be used and distributed without restriction    
-- provided that this copyright statement is not removed from the file 
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose: VHDL package containing a synthesizable CRC function
--   * polynomial: (0 2 4 5)
--   * data width: 8
--                                                                     
-- Info: [email]tools@easics.be[/email]
--       [url]https://www.easics.com[/url]                                  
-----------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

package PCK_CRC5_D8 is

  -- polynomial: (0 2 4 5)
  -- data width: 8
  -- convention: the first serial data bit is D(7)
  function nextCRC5_D8
    ( Data:  std_logic_vector(7 downto 0);
      CRC:   std_logic_vector(4 downto 0) )
    return std_logic_vector;

end PCK_CRC5_D8;

library IEEE;
use IEEE.std_logic_1164.all;

package body PCK_CRC5_D8 is

  -- polynomial: (0 2 4 5)
  -- data width: 8
  -- convention: the first serial data bit is D(7)
  function nextCRC5_D8  
    ( Data:  std_logic_vector(7 downto 0);
      CRC:   std_logic_vector(4 downto 0) )
    return std_logic_vector is

    variable D: std_logic_vector(7 downto 0);
    variable C: std_logic_vector(4 downto 0);
    variable NewCRC: std_logic_vector(4 downto 0);

  begin

    D := Data;
    C := CRC;

    NewCRC(0) := D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor C(1) xor 
                 C(2);
    NewCRC(1) := D(6) xor D(5) xor D(3) xor D(2) xor D(1) xor C(0) xor 
                 C(2) xor C(3);
    NewCRC(2) := D(7) xor D(6) xor D(5) xor D(3) xor D(1) xor D(0) xor 
                 C(0) xor C(2) xor C(3) xor C(4);
    NewCRC(3) := D(7) xor D(6) xor D(4) xor D(2) xor D(1) xor C(1) xor 
                 C(3) xor C(4);
    NewCRC(4) := D(7) xor D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor 
                 C(1) xor C(4);

    return NewCRC;

  end nextCRC5_D8;

end PCK_CRC5_D8;

Can anyone tell me how to reason out NewCRC(0)~NewCRC(4).

and what principle it is?

thanks
 

Re: CRC Problem

Search using google for "parallel crc" OR "fast crc".
 

Re: CRC Problem

Refer the following pdf.

Here u can find answer for your query.
 

    addn

    Points: 2
    Helpful Answer Positive Rating
Re: CRC Problem

One more good reference is following book you will
find it on this FORUM.

"Complete Digital Design A comprehensive guide to
digital electronics and computer system architecture"
by Mark Balch

Page 200-201
Hope this will clear all ur doubts!
 

    addn

    Points: 2
    Helpful Answer Positive Rating
Re: CRC Problem

here is one on parallel crc. it explains why the equations are framed the way they are.
 

    addn

    Points: 2
    Helpful Answer Positive Rating
Re: CRC Problem

this post explains the reason behind the equations.
 

Re: CRC Problem

this will help u out
 

    addn

    Points: 2
    Helpful Answer Positive Rating
Re: CRC Problem

hi, friends

thank for your reply.

and my another question is

can the way of parallel CRC or look up table CRC

apply to variable length of data??

thanks
 

Re: CRC Problem

Hi addn.,

For parallel CRC, variable data length is not possible.
 

CRC Problem

I need SPIE articles about IR seekers.
 

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