Timing analysis : critical warning ! Help me please....

Hi !

I'm currently performing an implementation on an FPGA with Quartus II and I have a problem with timing analysis relating to setup time, hold time and negative slack. I would have liked to know CONCRETELY what actions I have to take in order to solve this because I know absolutely nothing about STA.

Thanks a lot !!!

Hi flyjuju2

Could you be more explicit?
How do you implement your clock or clocks?
In the Timing report you'll see what's happening.

With more detailed information perhaps...

Pont de Pedra said:

Hi flyjuju2

Could you be more explicit?
How do you implement your clock or clocks?
In the Timing report you'll see what's happening.

With more detailed information perhaps...

Click to expand...

I actually have many setup time violations and hold time violations (more than 200). I guess that the problem comes from the fact I use an integrated PLL (altclklock function) provided by altera for APEX boards (I use this in order to multiply the original clock by 3, to 'sample' an incoming signal at this frequency ,to finally regenerate the external clock that sent our data, this new clock feeding my design). Without this PLL, it behaves correctly... How can I get rid of all of these violations ?

hi flyjuju2,

Just want to share with u a note on STA.
As for ur prob, I'm not familiar wit Altera Apex board. Sorry


regards,
no_mad

ps: the Quartus Timing Analysis doc u can get on altera website.

Hi flyjuju2:
Let's focus in the hold time violations. Then you can start reading the report Timing Analyzer.

Something in red? Probably the problem starts with the output of your PLL.
Have you assigned it as a Global Clock?
And what about your input clock?

After that, you can try enlarge the hold time with the assignments in that clock as you can see in the pictures (Multicycle Hold = 2). Try different values (2,3,5,6) if necessary.

The pictures are only as a guide, I have not seen your design.

If you have still problems, report them again.

Hope this helps.

Pont de Pedra

also, try to enable WYSIWYG option
goto assigment -> settings -> sythesis netlist optimozation and check all three boxes

Good luck

Allright, I'm back and still with some hold violations !
So I tried Pont de Pedra proposals, especially the clock specifications and it solved a lot of the violations. I didn't apply any multicycle constraints because I'v heard that it had some functionnal consequences. Thanks a lot for the print screen it helped a lot !!!
I also tried Iouri suggestion with WYSIWYG option and it didn't resolve nothing more unfortunately.
Any other idea what I could do more for getting rid of the last violations ?

I can maybe explain you a little bit more my design : so I have an incoming data which I sample 3 times faster than the board clock ie at 100 MHz. With this sampling, I extract the willing data and an enable write signal thanks to an FSM. Then I send my enable write signal onto a 2nd PLL which allows me to reconstitute the clock which had originally sent my incoming data. The final aim is to have the 2 APEX boards which communicates together some data.

OK show you souurce code, sounds like yiu need to organize pipelines

Hi:
Could you post the Timing Analizer_Summary?
What device are you using exactly?
As Iouri says, without your design, it isn't easy.

Regards

Pont de Pedra