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Parse a VHDL string array

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rzsmith

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I would like to parse separate characters inside a VHDL string array. The actual code is quite large and 99.99% of it has nothing to do with this question.

I am getting an error: Error: Indexed name is not a 'std_logic_vector'

Sample code:

component TestRun is
port ( StrAr : in string(1 to 3) :="ABC" );
...
signal Char_Two : std_logic_vector( 7 downto 0 );

What is the correct syntax to:

Char_Two <= StrAr(1); -- ie Char_Two = 'B'
 

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Hi,

Any editor that can work with "regular expressions" should do.

What OS are you using?

Klaus
 

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The string type in VHDL is defined as:
Code VHDL - [expand]
1

type string is array(positive range <>) of character;


The Character type is an enumerated type containing all 256 ASCII chars.

So a character cannot be assigned to a std_logic_vector, because they are not the same type.
You will need some form of conversion between the two. The way I would do this using the numeric_std package is:

Code VHDL - [expand]
1

Char_Two <= std_logic_vector(to_unsigned(character'pos(StrAr(1)), 8));
 
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    jenish

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KlausST said:
Hi,

Any editor that can work with "regular expressions" should do.

What OS are you using?

Klaus
Click to expand...
I am using both Windows and Linux. I am familiar and use regular expressions in Linux commands, but was not aware that RE are available in VHDL.
 

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Hi,

I guess I misunderstood what you want to achieve.....

.. but RE do not belong to any "specific language". You may use them an any text based file.
You may use them for German, English, C, python, scripts, batch files ....

Klaus
 

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Code VHDL - [expand]
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component TestRun is
port ( StrAr : in string(1 to 3) :="ABC" );
...
signal Char_Two : character;
 
Char_Two <= StrAr(2); -- ie Char_Two = 'B'


You don't mean synthesable design, right?
 

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niciki said: 
Code VHDL - [expand]
1
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3
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component TestRun is
port ( StrAr : in string(1 to 3) :="ABC" );
...
signal Char_Two : character;
 
Char_Two <= StrAr(2); -- ie Char_Two = 'B'


You don't mean synthesable design, right?
Click to expand...
 

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TrickyDicky said:
The string type in VHDL is defined as:
Code VHDL - [expand]
1

type string is array(positive range <>) of character;


The Character type is an enumerated type containing all 256 ASCII chars.

So a character cannot be assigned to a std_logic_vector, because they are not the same type.
You will need some form of conversion between the two. The way I would do this using the numeric_std package is:

Code VHDL - [expand]
1

Char_Two <= std_logic_vector(to_unsigned(character'pos(StrAr(1)), 8));
Click to expand...
That solved the problem. Thank-you for your post, it really helped me out.
 

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