sizing up of a transistor?

increasing transistor rout

Dear all,
During digital design, what's the effect of sizing up a transistor? If the transistor is sized up by increase its width, it's capacitance will increase while the resistance will decrease. So the total RC delay remains almost unchanged,am I right?

When you talk about sizing, it must be a chain of transistors and the purpose of sizing is to make the minimum delay of the whole chain.

I think it would be accurate to distinguish sizing up a "transistor" and sizing up a "gate".

-- When you size up a CMOS gate ( which consists NMOS PDN and PMOS PUN), you increase its driving capability but also increase the capacitive load to previous gate. This will affect the total delay of the logic chain. This is so called "gate sizing" for digital designers to do timing optimization. For this topic, google "logical effort" for more information. David Harris has a nice book titled "logical effort" on it.

-- In CMOS, you can do transistor sizing within the gate to tune the performance of the gate, for it'll affect the threshold voltage and delay of the gate.

-- In dynamic logic such as domino logic, there is a feeder at the output of the gate. The feeder keep the gate from the harm of charge sharing. But typically you need to size up the feeder so that it won't fight with the PDN during the evaluation.

Anyone know other cases please continue.

Hi don_quixote,
Just as you said, the sizeup of transistor will affect its threshold and delay time. What I want to know is, if I size up a transistor, it will have capacitance increased and resistance decreased, then how about its intrinsic delay that concerns about RC product?

I think there are two points of view to this problem. If we have a gate driving a load capacitor with a fixed value which is higher than the parasitics of the gate at the output, then increasing the sizes of the transistors increases the driving ability of the gate and hence the speed. But if we continue increasing the sizes, eventually the parasitics from the transistors will become dominant and at this point further increase in the size will not bring noticable increase in speed.

eexuke said:

Dear all,
During digital design, what's the effect of sizing up a transistor? If the transistor is sized up by increase its width, it's capacitance will increase while the resistance will decrease. So the total RC delay remains almost unchanged,am I right?

Click to expand...

u are correct only to a certain extent.the change in capacitance and resistance cannot be on equal scales.the method increasing transsitor sizes to reduce the resistance will work only till the point when the load capacitance is not dominated the drain diffusion capacitances.once this point is crossed the reduction in delay will not be appreciable,infact the delay may increase.this effect when the transistor size in increased beyond a limit leading to high o/p capacitance thus leading to increased delay is termed as "self loading".

regards
amarnath

eexuke said:

Hi don_quixote,
Just as you said, the sizeup of transistor will affect its threshold and delay time. What I want to know is, if I size up a transistor, it will have capacitance increased and resistance decreased, then how about its intrinsic delay that concerns about RC product?

Click to expand...

Hi, eexuke,

The delay of a gate typically is determined by
- the input signal slope
- output resistance
- load capacitance

Now let's ignore the first item. Output resistance (Rout) is roughly inverse proportional to its
size.
Load capacitance = the diffusion cap of gate it self (Cdiff) + wire cap of the output connection (Cwire) + gate cap that the gate drives (Cl).

Intrinsic delay = 0.69*Rout*Cdiff

Cdiff is proportional to gate size. So basically the intrinsic delay of a gate is irrelevent of its size. amarnath is right that the linear dependency of Rout and Cdiff on gate size is not exact, but in digital circuit we can roughly assume so.

As you can see, increasing the gate size surely decreases the delay due to Cwire and Cl, but the gate exhibits large cap to previous gate. So there is a balance. That's what logic effort comes for.

If you individually tune the transistor size within a gate, the VTC curve will shift. The gate delay is the average of pull-up delay and pull-down delay. In digital circuit we roughly maintain a 2~3 ratio of P/N transistors to get the best average delay. Stray from that, the gate typically get slower, and more susceptive to noises.