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How to use multiple clocks in a VHDL based data path?

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nashafi

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vhdl multiple clocks

Hi,

I am designing a decimation filter for a data standard like ardis or mobitex.
since there is a lot of upsampling and downsampling going on so i need multiple clocks all the way in my pipeline.
How can i write different clocks for my test bench. I am confused about how can i associate different frequencies with different components in my top file


Thanks,

-Nauman
 

datapath vhdl

xilinx FPGA's offers multiple clock inputs u can use them all at the same time,

xilinx FPGA's also contains a DLL which can be used to divide a clock or multibly it by a factor or even create a phase shift from the input clock.

check out xilinx spartan2 FPGA's they are really good.
 

multiple clocks vhdl

In the testbench the frequency is not the problem.
In one data pipeline the clock frequency have to be a single one.
When 2 pipelines with different frequencies are connected together
2 situations occur.
When one frequency is equal to multiplied second frequency,
or the frequencies have small common divident
then
both pipelines must have a single frequency which is highest of them,
or can be divided to both of them.
When the frequencies have the great common divident,
then
an FIFO buffer is introduced which consists of 2,3 or higher latch stages.
For example f1=2 MHz, f2=3 MHz then
the common frequency is 6 MHz which is their divident.
 

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    nashafi

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