How to reduce resistor variation effect for constant current reference

Hi all,
I am designing a constant current reference generated by bandgap voltage.
The equation are IREF=VBG/R(poly)
but check with the foundry model , the R variation is 20% in TT-SS corner.
How to reduce the resistor variation effect or make a compensation ?
Thank you in advance...

Regards,
ejcmos

ejcmos said:

Hi all,
I am designing a constant current reference generated by bandgap voltage.
The equation are IREF=VBG/R(poly)
but check with the foundry model , the R variation is 20% in TT-SS corner.
How to reduce the resistor variation effect or make a compensation ?
Thank you in advance...

Regards,
ejcmos

Click to expand...

Check this it is helpful

https://www.jstage.jst.go.jp/article/elex/8/19/8_19_1602/_pdf

A simple solution..
Variation is Inverse proportional to Resistance Dimensions.So, larger Resistances exhibit lower variations.
Paralleling larger Resistances equal to target resistance will exhibit lower variation.Also, tying active regions of these resistances will also demonstrate lower mismatch effect.( prctical circuit)

hi,

Also, tying active regions of these resistances will also demonstrate lower mismatch effect.

Click to expand...

correct me if I'm wrong. I think mismatch is related to local variations whereas the 20% difference in process corners concerns global variations.

How to reduce the resistor variation effect or make a compensation ?

Click to expand...

I think this is a tricky topic. Practical voltage reference relies on resistor ratios for higher reproducibility since variations is minimized. But a current reference on the other hand, for example in bandgap i.e. I=Vtln/R, makes the topology rely on trimming.

There are a lot of articles that pursue reduced process variability in current references, e.g. https://link.springer.com/article/10.1007/s10470-013-0105-z however they are not simple solutions.

But from razavi's book: Design of Analog CMOS Integrated Circuits, he stated you can use switched-capacitors if you have an available clock source.

The question as old as IC design is.
You can do:
1. Trimming
2. Use external resistor
3. Switched Capacitor
4. Invent circuit which will use ratio of resistors and bandgap voltage instead of resistor absolute value.

Good luck!

Selection, sizing, trimming are all there is.

Big resistors have only the process & temp variations.
Narrow / short resistors pick up lithographic systematic
error (over/under-expose, over/under etch of hard-mask
oxide leads to delta-W) along with more sensitivity to
local variation (mismatch).

Each resistor type will have its own doping and litho
induced variations.

What the fab rats say is their variation, is really the
variation limits that allow them to ship whatever
comes out of the far end of the pipe. Designers are
supposed to eat it, and design management is usually
too wimpy to push back "just for one part" (never
mind the next and the next). So you get to design
to 4-sigma limits while the fab is on the hook for
three and accepts very little tasking to reduce the
sigma itself.

Absolute accuracy is going to want trimming.