2 layer layout trouble - please help

2 layer layout help

I am having trouble laying out my 2 layer board.. I have attached a jpg and the Protel PCB file that I'm using. My problem is that I don't know if it will be stable enough.. there's nothing too high speed on it (RS 232 and a FTDI USB chip). I have been reading High-speed digital design by Johnson, and in one section, he recommends using one layer with horizontal power stripes across hte whole board, and the other layer having perpendicular ground stripes (and placing components in between). Is this method much better than what I have? I submitted my file for quote, and the PCB guy saying I would be better off fitting all teh components on the top layer, and using the bottom for a solid ground plane. However, I don't see how I will be able to route all the signals on the top layer!! Any suggestions?

Re: 2 layer layout help

This is one of those situations where a ground pour on the top and bottom layers would probably give you the best results. It would provide the shortest return paths for signals on both sides, and should give you the quietest board. This is all said without knowing exactly what your circuit is supposed to do.

If you have both analog and digital circuitry on this board, you will want to ensure that the signal return paths through the ground copper are not shared by the two signal types. This can be done by splitting the pour into regions, if necessary.

Recognize that you will not have controlled impedance in general; however, you could adjust the trace width and spacing to the ground pour for any trace that needs to be a specific impedance.

I attached your board, modified with the copper pour so you can see what I mean. Note that dead copper is removed to ensure that there are no regions that might be sources of resonant absorbtion or passive coupling.

2 layer layout help

Thanks for your suggestions... my circuit, on the right hand side of the board (with the bigger traces and bulky caps) is for high-current paths to a Polaroid ultra-sonic sensor. That thing draws up to 2A when in operation, so I tried to separate it and provide isolated return paths to GND. The right side ofthe board is just USB and RS232, and the middle a PIC. Also, regarding controlled impedanec, I don't need it, but how accurate is what you said?? I thought manufacturers have to specifically have controlled impedance capabilities in order for you to get reliable results?

Re: 2 layer layout help

"Controlled impedance" means that YOU (the board designer) are controlling the impedance of specific traces in order to ensure signal integrity. "Uncontrolled impedance" basically means you don't care about the impedance because the signal conditions don't warrant that concern.

All traces on a PCB are transmission lines. For critical signals above the audio range, the transmission line impedance should match the terminating impedance to ensure maximum energy transfer to the load. When there is an impedance mismatch, some energy is reflected from the point of mismatch. That reflected energy causes signal distortion.

An engineer designing a board will select the trace width, trace thickness, dielectric material, and distance to the return path to give the desired impedance. The factors affecting impedance are: trace width, trace thickness, trace cross sectional shape, distance between the trace and return path, and Er (dielectric permitivity - sometimes expressed as loss factor). The board fabricator will advise the desginer of any changes required to control impedance because of the Er for the particular batch of material they are using to make the board. They are also in the best position to know how their etching process will affect the cross sectional shape of the trace.

For low frequencies (DC-audio), the trace impedance is not a significant factor for signal integrity. Inductive coupling, capacitive coupling, and intermodulation are the greatest concerns.

With regard to your design - you are correct that the high current paths for the ultrasonic device should be kept separate from the other circuitry. Your PIC is a digital device operating at radio frequency (RF). The clock, and digital I/O are susceptible to false triggering from digital signal distortion that might be caused by inadvertently coupling a portion of the ultrasonic signal into a digital pathway.

The copper pouring I suggested is still a good idea - you just need to adjust the pour around the digital pathways, and your high current signal paths, such that they keep the two different types of ground returns separated.

Re: 2 layer layout help

Thanks for that great explanation.. having just read Johnson's chapter on Transmission lines, I was aware of all that, but I thought that the board manufacturer has to be able to control all the parameters required for controlled impedance traces (dielectric material, thickness, loss factor, all the things you mentioned).

I will pour a GND plane over, and separate the sensor return paths and digital ones. I will then repost. AGain, thanks for your help!

Added after 1 hours 6 minutes:

I have updated the PCB with repoured copper, and I split the ultrasonic and digital sections. Let me know if there are any other improvements that I can potentially make!

Re: 2 layer layout help

You selected not to pour over existing ground when you did the polygon pour. The result is isolation of the signal return path on the pour, so it has very little beneficial effect. All you did was float a ground around the existing ground traces.

I suggest that you let the copper pour carry the signal returns between chips instead of forcing them to go through the power supply traces.

The idea behind the copper pour is to provide the most direct, lowest inductance, return path for your signals. As you now have it, it doesn't carry any signal information between the elements of your circuit. The way it floats, it may even increase crosstalk because it appears as the plate of a giant capacitor that runs adjacent to most of the signals. All of the adjacent signals will couple to the common plate and try to send current back to the plate's ground point.

Try to visualize the signal going from one chip to another. The trace that connects the two pins is only one half of the complete circuit between the two chips. The other half of the circuit is through the ground, or power, connection to each chip. Your goal should be to provide the best possible direct connection between the two chips for BOTH halves of the circuit. Every signal is a LOOP - make the physical copper loop as small as possible, or electron physics will try to do it for you by inductive and capacitive coupling in places you don't want it.

2 layer layout help

...doh, of course that makes sense. I poured the copper and didn't even check if it poured over the ground nets!! Can you tell this is the first time using pours Thanks for your help, I will give this board a try and see how it holds up!

Re: 2 layer layout help

Hi Jai
There're really many problem in your GND pour. The polygon on bottom layer is invisible, the clearence is too small, the track width of polygon is only 1mil, and the "pour over same net" should be checked...But they were all fixed :-0
mike

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www.ezpcb.com

2 layer layout help

Thanks Mike.. my first time pouring, so i will get it right eventually

2 layer layout help

jdhar,
Some observations: at the DB9 connector, if the pin numbering is correct, you mirrored the signals. Pin 5 is gnd, and pins 2 and 3 are signal lines. At the USB connector, I see the 5V pin is free. Even if the system is not bus powered, you have to connect the 5V pin from USB connector, in order to ensure the reset of the ftdi chip. Check its datasheet, there is an application example there for this case. I would not reccomend to tie the reset of the FTDI to the reset of the CPU. The CPU must be reset at the power on (or whenever you consider), but the FTDI must be reset when you plug in the USB cable. It is not necessary to reset it at the same time with your CPU. I would also reccomend to tie the USB and serial DB9 shields to GND. Also, you tied the pin 30 directly to digital power supply. This is an analog supply pin. This pin powers a PLL inside a chip, and must be connected as in the datasheet, otherwise the digital noise may cause problem to your FTDI, and you may encounter strange problems at the USB communication.

/pisoiu

2 layer layout help

Thanks for your feedback pisoiu... definitely helpful. Looks like I have some rework ahead

Regarding the DB9, it's intentionally mirrored. The pin number isn't correct, which is why it's mirrored. I just used a std footprint from Protel, and didn't feel like renumbering the pins.. I made the mistake before of following the pin number in the footprint, and it ended up backwards. I will eventually get around to redoing the footprint.
- About the USB controller, I completely missed the section regarding the PLL supply. Definitely something I will have to correct. And about grounding the case, I don't know enough about shielding and chassis ground, so I just left it unconnected. Perhaps a resource on grounding cases may help??