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Looking for references about viterbi decoder

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chuenwan

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Question viterbi decoder

K = 7 , code 1/2
we need 64 states CSA for full parallel,the size of the adder/subtractor is 11 bit .

Is it too big for this design?

any source for reference to me?

thx
 

Re: Question viterbi decoder

The file is removed.
 

Re: Question viterbi decoder

Give me a couple of days and I dig it out from my CDs.
 

Re: Question viterbi decoder

SIMD Viterbi Decoder provides library functions to decode certain popular error correction codes.

version supports two codes: a rate 1/2, constraint length 7 (r=1/2, k=7) code, and an r=1/2, k=9 code. Four implementations of each decoder are provided.
One is in portable C and should run in any GNU C environment.

The other three use the IA32 SIMD (single instruction, multiple data) instruction sets: MMX, SSE, and SSE2. The SSE version of the k=7 decoder executes at ~9 megabits/sec on a 1GHz Pentium-III.

I shall upload some source for this viterbi decoder.
 

Re: Question viterbi decoder

I managed to find the virtebi from CD. I hope this will help.
 
Question viterbi decoder

got it, thx
 

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