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In digital logic simulation, a delta cycles are evaluation of expressions, followed by value updates, causing more evaluations, and more value updates, and so on. Each time through the loop is one delta cycle. Different languages have specific definitions of what can happen in a delta cycle, and in most cases, simulation time does not advance in a delta cycle until there is nothing left to do at the current simulation time. Then simulation time is stepped to the next scheduled activity. So there can be one or many delta cycles in a time step. This is the case for SystemVerilog and VHDL.
So can I say that in verilog, if I use `timescale 10s/1s, there are 10 delta cycles in a time step? if I ues `timescale 1s/1s, there is only one delta cycle? Thanks.
In digital logic simulation, a delta cycles are evaluation of expressions, followed by value updates, causing more evaluations, and more value updates, and so on. Each time through the loop is one delta cycle. Different languages have specific definitions of what can happen in a delta cycle, and in most cases, simulation time does not advance in a delta cycle until there is nothing left to do at the current simulation time. Then simulation time is stepped to the next scheduled activity. So there can be one or many delta cycles in a time step. This is the case for SystemVerilog and VHDL.
No. There can be an infinite number of delta cycles in a time step because a delta cycle does not have to advance time. However, most simulators will place a limit on the number of delta cycles to help debug infinite loops.
`timescale has nothing to do with delta cycles except that the precision defines the smallest possible time-step you can take. `timescale is used to determine how time is represented as an integer internally to the simulator.
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