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worst case corners definitions

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Junus2012

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Dear friends

I am simulating my circuit with worst corners
the worst corners defined in my technology ar

wp = worst case power = fast NMOS & fast PMOS
ws = worst case speed = s slow NMOS & slow PMOS
wo = worst case one = fast NMOS & slow PMOS
wz = worst case zero = slow NMOS & fast PMOS

kindly what is the meaning of fast and slow ????

I have also second question

if I am using the monticarlo simulation, how much percent of the right value should be in order to say that the design is ok ??


Thank you in advance
 

fast means higher threshold voltage and slow lower threshold voltage

monte carlo... upto 3 sigma
 

so faster and slower only related to the Vth ??????

if iti is like that then simulating the design with corner analyses will not cover the parameter variability in the wafer, and hence it is not trust method to predict the success the design practically


erikl said:
Just the other way round, Emma! Lower Vth means faster switching on, resp. larger Id.



±3σ means 99.7% , s. the Gauss' standard distribution. Scroll down to "Standard deviation and tolerance intervals" and see the text below the blue curve.
Click to expand...
 

Junus2012 said:
so faster and slower only related to the Vth ??????
Click to expand...
Essentially, yes. For process variations, you have more parameter variations which affect the speed corners, like, e.g. tox.

Junus2012 said:
... simulating the design with corner analyses will not cover the parameter variability in the wafer, and hence it is not trust method to predict the success the design practically
Click to expand...

That's why fabs/foundries (should) provide different MC variation sets for mismatch (one wafer only) and for process (all wafers).
 
But Erikl, I am working with SOI technology from XFAB and they only provided me those corners models. and I was thinking that if the design passed theses corners it is somehow comparable to 99% of monecarlo until you told me the truth .... I am now a little sad

erikl said:
Essentially, yes. For process variations, you have more parameter variations which affect the speed corners, like, e.g. tox.



That's why fabs/foundries (should) provide different MC variation sets for mismatch (one wafer only) and for process (all wafers).
Click to expand...
 

Junus2012 said:
... I was thinking that if the design passed theses corners it is somehow comparable to 99% of monecarlo
Click to expand...

May be you actually got the process parameter variation set (i.e. the variations over many wafers). And perhaps the mismatch variations are already included? Ask them!

And a ±3sigma parameter variation MC success means >99% good chips.
 
Junus2012 said:
But Erikl, I am working with SOI technology from XFAB and they only provided me those corners models. and I was thinking that if the design passed theses corners it is somehow comparable to 99% of monecarlo until you told me the truth .... I am now a little sad
Click to expand...

You can expect that the performance spread over process corners is similar to +-3sigma process MC spread if your circuit is a standard logic gate. That's because the speed of logic depends on maximum Idsat and the process corners were created to show the extreme values of Idsat.
Whereas if your circuit performance depends on analog small signal parameters such as rds, Cgs, ... then you may see a large difference between process MC and process corner run.
Secondly, process corners do not contain correlation information. You can mix corners of resistors, BJT and MOS at will; but many of these mixed corner combinations are physically impossible and useless to simulate. Process MC instead allows to correlate devices. So, if your circuit contains HVT and LVT MOS and/or moscaps, then again process corner run and process MC run may return very different results.

This is not related to local MC (mismatch MC). You can mix local MC with process corner, or can mix local MC with process MC.
 
I am simulating an analog circuit

micpro said:
You can expect that the performance spread over process corners is similar to +-3sigma process MC spread if your circuit is a standard logic gate. That's because the speed of logic depends on maximum Idsat and the process corners were created to show the extreme values of Idsat.
Whereas if your circuit performance depends on analog small signal parameters such as rds, Cgs, ... then you may see a large difference between process MC and process corner run.
Secondly, process corners do not contain correlation information. You can mix corners of resistors, BJT and MOS at will; but many of these mixed corner combinations are physically impossible and useless to simulate. Process MC instead allows to correlate devices. So, if your circuit contains HVT and LVT MOS and/or moscaps, then again process corner run and process MC run may return very different results.

This is not related to local MC (mismatch MC). You can mix local MC with process corner, or can mix local MC with process MC.
Click to expand...
 

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