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Assign fix values in vhdl

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sheikh

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Hello Dears
How can I use fix values and coefficients in vhdl? Does these fix values synthesisable? For instance in equation "Y= 23X" , Is it enough to write :

Code: 
Signal a :STD_LOGIC_VECTOR :=  (0=>'1', 1=>'1', 2=>'1', 4=>'1', others=>'0');
......

y<= a*X;

I did it in my code and the simulation result was ok, But in RTL schematic the port that related to this value eliminated from multiplier and Ise shows this warning:
"Signal <a> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000010111.

Is it a problem for real implementation? ( I mean on FPGA)
Also, it happen when I put some fix values at the input of MUXes.

Regards
mostafa
 

If fixed value is provided on S input of MUX then MUX will get optimized. It is not a problem for real implementation.
 
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    sheikh

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Thanks Dear dftrtl
So I can consider " signal" for this kind of values ( I mean, fix values ) and use them in my code without any worry for hardware implementation. true!
 

If these values are constant, why not use a constant instead of a signal?

constant a : integer := 10;
 
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    sheikh

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Thanks TrickyDicky, Yes they are constant, Does constant synthesis able? Also, Could you please tell me, what is the differences between assign fix values by "signal" or by "constant" in a real implementation? (I mean From hardware view).
Thanks in advance
Mostafa
 

There is no change by having a constant signal or constant itself.
 
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