Zampradeep
Newbie level 4
..hi guys..others project is time code generator on fpga and generated time code ....now have to do pwm....here is the code i wrote but not getting output...in code i used /100 counter as actual serial data and /10 to compare it and change duty cycle.....i.e each serial data pluse time=10 times /10 counter output pulse width..given code has some unused signals ignore it....i want siganl of 20% duty cycle...
sorry if any silly mistakes....i am complete newbie to vhdl....should i use /5 conter instead of 10
sorry if any silly mistakes....i am complete newbie to vhdl....should i use /5 conter instead of 10
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pwmm is port(cp,reset : in std_logic; dout :out std_logic ); end pwmm; architecture pwmm_arch of pwmm is signal divby100: std_logic_vector(3 downto 0):="0000"; signal divby10: std_logic_vector(3 downto 0):="0000"; signal count: std_logic_vector(3 downto 0):="0000"; signal count2:std_logic_vector(3 downto 0):="0010"; signal count5:std_logic_vector(3 downto 0):="0101"; signal count8:std_logic_vector(3 downto 0):="0100"; signal div100: std_logic_vector(3 downto 0):="0000"; begin process(cp) BEGIN if(cp'event and cp= '1') then if (divby10="1001") then divby10<="0000"; if(divby100="1001") then divby100<="0000"; div100<=div100+'1'; else divby100<=divby100 + '1'; end if; else divby10<=divby10+'1'; end if; END IF; end process; process(div100(0)) begin if(div100(0)'event and div100(0)='1') then while (COUNT2 > COUNT) loop IF divby100(0)'event and divby100(0)='1' THEN COUNT<=COUNT + '1'; dout<='1'; end if; end loop; dout<='0'; COUNT<="0000"; END IF; END PROCESS; END pwmm_ARCH;
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