Relation between voltage and setup time ?

Is their any relation b/w voltage and setup time n hold time. If i increase or decrease voltage , will it affect setup time , and also does temperature have any affect on setup n hold time ????

Obviously, they will definitely effect the setup and hold times of a cell, a particular cell will have different setup and hold values for different operation conditions (Voltage, Temperature)..

but how will it effect ? functionality of a cell will change with change in operating conditions , but how? if i change volatge , why setup n hold time change . whts the relation between them .

sharif.shiek said:

Obviously, they will definitely effect the setup and hold times of a cell, a particular cell will have different setup and hold values for different operation conditions (Voltage, Temperature)..

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jeet_asic said:

but how will it effect ? functionality of a cell will change with change in operating conditions , but how? if i change volatge , why setup n hold time change . whts the relation between them .

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If you know how setup time of a cell is calculated, i mean on which basis setup time of a cell is defined, then you can get that answer easily..try it...

Voltage is inversly proportional to delay of a cell. (My words.. plese correct if wrong )

Voltage is inversly proportional to delay of a cell. (My words.. plese correct if wrong )

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It is other way. Delay is inversely proportional to Voltage.

Hello,

Sir , how does delay decrease or increase inversely w.r.t to increase or decrease in Voltage. Both of these do have inversely proportional relation , but i am little curious to know the reason behind this . I have a theory , don't know whether i am correct or wrong , pls correct me if i am wrong .

As we increase voltage , electrons in valence band acquire more energy and jump to conduction band , thus increase in current and decrease in resistance . Since (delay) T (tou) = RC , as R decrease Delay also decreases . Is my thinking process correct. I am feeling that i am mixing net delay with cell delay calculation , since net delay is given by RC .

help me out from this puzzle .

yadavvlsi said:

It is other way. Delay is inversely proportional to Voltage.

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yadavvlsi said:

It is other way. Delay is inversely proportional to Voltage.

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So silly of me

I think voltage increases definitely the delay increases, because if voltage increases it will take more time for transition from low to high and high to low, so i think the delay and voltage are directly proportional... (I think this is why the LVDS have low voltage like 2.5v ,etc... for rapid transaction and to eliminate the delay)... Please correct me if wrong...

I think the answer for the main problem here is that there is no relation between voltage and setup/hold time.
setup/hold time depends on input D pin slew and clock pin slew.

as far as delay is concerned cell delay increases with decrease in voltage. Current will decrease as resistance is constant and it will take more time to charge the load capacitance and same in the opposite case with increase in voltage current will increase hence delay decreases.