Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] SLV into System Generator Block

Status
Not open for further replies.
ravics

ravics

Advanced Member level 4
Joined
Sep 1, 2010
Messages
116
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,298
Location
Shangri-la
Activity points
1,852
How can I input std_logic_vector into system generator blocks? Constant block supports fixed, boolean & dsp instructions. Is there any way to force slv as input to another sysgen blk?
 

I'm not sure I understand your question... any time you us a multi-bit bus in SysGen, it will be std_logic_vector. Otherwise, you can likely meet your needs using a black box.
 
  • Like
Reactions: ravics

    ravics

    ravics

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top