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[SOLVED] vhdl code to obtain 2^n for the input n can u help me plssssssss

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sushma67

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library ieee;
use ieee.std_logic_1164.all;
entity shf is
port(I:in std_logic_vector(2 downto 0);Y:eek:ut std_logic_vector(7 downto 0));
end shf;
architecture behaviour of shf is
begin
Y<=2^I;
end behaviour;
 

If your input is only three bits wide, you could easily implement this using a lookup table:

000: Y <= 8'b00000001;
001: Y <= 8'b00000010;
010: Y <= 8'b00000100;
011: Y <= 8'b00001000;

etc.
 
Several errors:

1. there is no ^ operator. The power operator is **
2. A std_logic_vector is not a number, therefore you cannot use it directly in arithmatic.

use ieee.numeric_std.all;

Direct power code:

Y <= std_logic_vector( to_unsigned( 2 ** to_integer( unsigned( I), 8 ) ) );

Or how about thinking of a shifter:

Y <= std_logic_vector( x"01" sll to_integer(unsigned(Y)) );

They should both give the same hardware results.
I Highly recommend you synchronise your design!
 
set y to all zeros(reset y to zero) and the make the Ith position high.

y[7:0] <=00000000;
//i is given by input;
y[ i ]<=1;
 

arunbv123 said:
set y to all zeros(reset y to zero) and the make the Ith position high.

y[7:0] <=00000000;
//i is given by input;
y[ i ]<=1;
Click to expand...

Or in VHDL (as the OP asked for)
Code: 
process(I)
  variable i_temp : integer;
begin
  Y <= x"00";
  i_temp := to_integer( unsigned(i) );
  Y(i_temp) <= '1';
end process;
 

in verilog
assign Y = (1 << I);

i do not use vhdl. but i believe vhdl has similar operation.
 

for direct one and for the shifter also it is showing error that it is expecting ')' i tried ..... in the shifter what is"sll" i dint understand that
 

sll = shift left logical, and is available on arithmetic type signed and unsigned in the numeric_std library. Basically it is a multiply by 2^n, where n is the right number:

op <= a sll 6;

is the same as
op <= a * (2**6);

What code are you having an error with. You should be able to fix a simple syntax error yourself. Please post the code you're having problems with.
 

library ieee;
use ieee. std_logic_1164.all;
use ieee.numeric_std.all;
entity shf is
port(i: in std_logic_vector(3 downto 0);y:eek:ut std_logic_vector(15 down to 0));
end shf;
architecture behaviour of shf is
y<=std_logic_vector(to_unsigned(2**to_integer(unsigned(i),16)));
end behaviour;
 
Last edited:

first of all, you need to include the numeric_std library:

use ieee.numeric_std.all;

secondly, dont put spaces in the middle of code:

unsigned not unsi gned
 

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