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hi jeffsky520
thanks for your reply ,i think this error is linear error ,and it will not cause nonlinearity.but for example if my cap has a 1%mismatch ,it means that i input a 1V voltage then my S&H can only get 0.99V,how can i get 12bit resolution?
can i change my input ,for example...
hi everyone
i can not understand why cap mismatch is not so important in S&H design?
if i want to design a 12bit or more resolution pipelined ADC,but my cap can not so match(0.1%),is this a big problem in my S&H design?
thanks a lot
hi everyone
i have two question :
1) if i want to design a 12bit or high reslution ADC ,how can i generate the reference,can RES have really good mismatch (<0.01%)?
2) if use Flip-around THA ,then SH will have no cap mismatch problem?and cap mismatch will not introduce the ditortion?
thanks
hi everyone
i have two question :
1) if i want to design a 12bit or high reslution ADC ,how can i generate the reference,can RES have really good mismatch (<0.01%)?
2) if use Flip-around THA ,then SH will have no cap mismatch problem?and cap mismatch will not introduce the ditortion?
thanks
bandgap bias
hi guys
i have a problem about the bandgap bias ,it contains a OP and bandgap core.my op is a two stage op with PMOS INPUT pair and second stage is a simple driving stage. and i want use the CTAT as my op's bias,how can i do without lower my op's gain. if i use a diode connect...
maybe my question is not clear enough,let me depict the question specificly.
as is show in the picture ,when i charge the cap (VOUT change form 0 to VDD)
my gatep is decreasing ,at the same time the gaten is increaing ,then there is a current path from pp14 to np4 and there is power loss .and...
i have designed a rail to rail op for LCD driver,i use the floating CLASS AB output stage ,but to my surprise ,the voltage between gate of NMOS/PMOS is not followed .so when i charge the cap ,|VGS|(PMOS) increase ,at the same time VGS (NMOS) is also increasing ,and when i discharge the...
thanks,0.5%--1%larger than Vin,my OP is a rail to rail op,it can works in common voltage about 1V---12.5V,and my supple voltage is 13.5V,but the question is in my common votage range ,my input voltage is smaller than my output voltage,i am really confuse ,i can not understand what is devison...
hi everyone
i have designed a rail to rail op as a unit gain buffer stage ,then i find my output voltage is a little larger than my input voltage ,i do not know why?
my gain is about 60DB-70DB,and the device works well
Bcz I think Vout=Vin*A/1+A,then my output voltage should be a little...
hi all
the amount of the reference spur ,in the 3rd order PLL is approxiantely
20log [square(2)*Icp*R*Q*Kvco/2*Fref]-20log[Fref/Fp1]
R is the res of loop fiter ,Kvco VCO gain,Fref reference frequency for PDF ,Fp1 loop fiter pole,Q is the phase offset
can anyone explain why ?
the equation...
hi everyone
when designing a source driver ,we usually use three or five order low pass filter as the output loading condition,i can not understand the circuit is just the module of panel,or just as a low psss filter?
thanks in advance
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