zxasqw123
Member level 1
hi everyone
i can not understand why cap mismatch is not so important in S&H design?
if i want to design a 12bit or more resolution pipelined ADC,but my cap can not so match(0.1%),is this a big problem in my S&H design?
thanks a lot
i can not understand why cap mismatch is not so important in S&H design?
if i want to design a 12bit or more resolution pipelined ADC,but my cap can not so match(0.1%),is this a big problem in my S&H design?
thanks a lot