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Recent content by zhipeng

  1. Z

    Tanner L-Edit, Current density check

    Anyone? In general, how do people check metal/via current density in layout? Thanks!
  2. Z

    Tanner L-Edit, Current density check

    How should I get started, to perform an electrical rule check of current density? I can manually annotate current on nets, how should I let the tool help me figure out whether I have enough metal wire width with enough margin, enough via at optimal positions? Thanks!
  3. Z

    Synthesis with multiple threshold libraries

    In Encounter RTL Complier, is it possible to specify the tool to use UVT (Ultra-high Threshold Voltage) standard cell library for module A and RVT standard cell libray for all other modules? Currently, I am using optLeakagePower in postroute stage of Place&Route. However, it seems that a...
  4. Z

    What is typical leakage reduction percentage by replacing RVT cells with HVT?

    Case solved. On this specific process, for leakage reduction, one uses UVT (Ultra-high Threshold Voltage) library, not HVT (High Threshold Voltage), to replace RVT.
  5. Z

    What is typical leakage reduction percentage by replacing RVT cells with HVT?

    What is typical leakage reduction percentage by replacing RVT cells with HVT, for a deep sub-micron process? Looking at the databooks of a 45nm std cell library, it seems cell leakage power of HVT is almost as 1/2 as of RVT. Even if I replace all cells by HVT, the leakage only get reduced by...
  6. Z

    What is meant by HVT & SVT cells in library?

    What is typical leakage reduction by replacing RVT cells with HVT, for a deep sub-micron process? Looking at the databooks of a 45nm std cell library, it seems cell leakage power of HVT is almost as 1/2 as of RVT. Even if I replace all cells by HVT, the leakage only get reduced by 1/2. Is that...
  7. Z

    if - case optimization in verilog

    They are behaviorally equal. After synthesis, the two will probably become structurally equal too. Eliminating the default else in CODE 1 or the default: in CODE 2 could be bad for you, if you don't want latches being synthesized for the codes...
  8. Z

    Cadence Encounter timing modeling commands

    Hello, I wonder what commands/methods people use to generate .lib for a design, and use it later for place and route at top level. I am using EDI 9.1, found the timing model commands have very limited documentation in fetxtcmdref.pdf. And I could not get write_model_timing and do_extract_model...
  9. Z

    Cadence Encounter do_extract_model

    Somehow if I do the following scripts on my design, somehow the two libraries, shaping_filter_setup.lib and shaping_filter_hold.lib are the same, except for some "max_capacitance" entries. Both have 125 as nom_temperature and 0.9 as nom_voltage, even though _hold.lib should have -45 as...
  10. Z

    Verilog-A Accuracy Settings

    I am using Verilog-A to generate a carrier-frequency stimulus to an power amplifier in virtuoso schematics, but saw a mysterious frequency shift in the stimulus when I run spectre simulation. It reduces to a basic test case where, parameter real omega = 2* `M_PI *20e9; ... V(pure_sine) <+...
  11. Z

    How to export a deisgn in Cadence Encounter and import to PrimeTime for SSTA signoff?

    Is it possible to export a placed&routed deisgn in Cadence Encounter, and import it into PrimeTime, and use PtVx/PtPx engines to re-check timing analysis and power estimation? Thank you.
  12. Z

    Cadence RTLCompiler, how to prevent re-synthesis of the same module

    Thank you very much, aravind! If the four encoders are uniquified, later in hierarchical P&R, is there a way to make the other three into clones of the master partition? what is the command to make the hierarchical cell into a clone partition of a master partition? I could not find the...
  13. Z

    Cadence RTLCompiler, how to prevent re-synthesis of the same module

    Say, in the top level verilog netlist, it instantiates four instances of the same module DECODER. After RTLCompiler has done elaborate and synthesis, they becomes instances of four differently-named modules, DECODER, DECODER_1667, DECODER_1668, and DECODER_1669. How do I prevent the same...
  14. Z

    SOC Encounter: Failed to place a cell at (x, y) for followpin creation

    sroute writes to the log many lines of the following, and then it fails to connect the power pads in the pad ring to the core... Failed to place a cell at (2847.200 2651.600) for followpin creation Failed to place a cell at (152.480 2653.280) for followpin creation Failed to place a cell at...
  15. Z

    Cadence RTL Compiler fails to do enough incremental optimization at large design

    Hi aravind, Thank you for the reply. The problem is, when I synthesize the top level, it runs with few incr_delay, but timing is not fixed... When I synthesize module A or B, many rounds of incr_delay in the log, at the end timing is almost fixed, critical path delay is about 400ps. When I...
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