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Recent content by zhangljz

  1. Z

    why I can not run tcl scripts in Soc Encounter ?

    Hi, I am using encounter for PnR, and I am trying to write a script of the flow. But it seems that the tcl doesn't work in encounter. Script like this: foreach cell [get_cells *readout] { puts $cell } If I type this in the gui command console, I will get just a "0x211" while if I just type...
  2. Z

    [SOLVED] can not see any module in encounter floorplan view, urgent

    Hi friends, I am using encounter 13.26 . After synthesis, I import the netlist/lef/lib/io/etc to encounter. But in the floorplan view, I can not see any module. Since I am trying to use Top-bottom hierarchical flow, and there are several modules in the design. I want to make one of them as a...
  3. Z

    QRC extraction failed with DEF

    Hello, I want to use QRC for extraction of a digital design. I saved .def file from soc encounter, and plan to extract rc. But I got such an error that it seems I can only use LEF or libgen. But I think DEF should be fine for extraction. Is there anything wrong ? Here is my command file. I...
  4. Z

    strange unconstrained path in Soc encounter

    Hi, I am using encounter for PR, and I tried a very simple design but found unconstrained path. the netlist for PR is : Only one flip-flop the constrain file is after I import the design, when I check" report_timing -unconstrained " I got 3 unconstrained points, including the clk, and...
  5. Z

    clock gating cell bound in SOC encounter

    Hi morris_mano, The technology is very old, and there is no ICG cell in the library, so I have to use individual latch + and .
  6. Z

    clock gating cell bound in SOC encounter

    Hi, I am using encounter for PR, and in the design there are many clock gating cells that are implemented with " LATCH+ AND" gates. After PR, I found that the LATCH and AND gates are separated far away, like 100um. Is there any way in encounter to restrict the distance between them? Thank you
  7. Z

    [Moved]: inverter with AMS simulation

    Hello, I am using AMS to try mixed signal simulation with two inverters: one is in analog with nmos/pmos, the other is in verilog with "assign out =~in;", and the analog inverter will drive the digital one. The plot is not very precise as expected that the digital output didn't rise or fall...
  8. Z

    how to avoid DRC violation in soc encounter when adding decap cells as fillers

    Hello navin, It works, Thank you.
  9. Z

    how to avoid DRC violation in soc encounter when adding decap cells as fillers

    Hello, At the end of PR, I need to add fillers in the deisng, and I prefer decap cells because they are helpful to IR drop. But since decap cells has metal1 inside, when I chose decap cells for filler adding, all the gaps are filled with decap cells which leads to many DRC shorts. It seems that...
  10. Z

    clock gating timing analysis with synthesized ICG cell

    Hi slutarius, Thank you for your reply. But will this cause violation? I mean the gator will cause some delay, but in the report the delay is not toke into account, because it directly use CLKA. Especially in P&R ( I haven't been to this step), since the delay will be even larger, if the...
  11. Z

    Is it necessary to do DFT on a MPW chip ?

    Hi all, Now I am designing a chip that with some logic circuits haven't been verified before, and we put it on a MPW. Since the design is not pretty sure if it is going to be working, do I need to do DFT ? or some other suggestions for test ? Thank you.
  12. Z

    clock gating timing analysis with synthesized ICG cell

    Hi, I made the module to be dedicated clock gating cell as it said on RTL compiler manual. And clock gating insertion works well. But the ICG cells seems to be transparent in timing report, because the flop valid_event_buf_reg[10] is clock gated, not directly driven by stop_HF, but in the...
  13. Z

    clock gating timing analysis with synthesized ICG cell

    Hi guys, I am using clock gating in cadence RTL compiler, but there is no ICG cell in the library. So I implemented an ICG cell with code, which is active high ICG cell module ICG_posedge( input ck_in, input enable, input test, output ck_out ); reg en1; wire tm_out, ck_inb; assign...
  14. Z

    connect all the clock gating test pins to a port in RTL compiler

    Hi, I am using RTL compiler for synthsise, and I want to implement clock gating. I don't have ICG cell, so I wrote a module as the clock-gating module, which has "ck, D,Q,enable, test", where test is the clock gating control signal. module ICG_posedge ( input ck_in, enable ,test, output...
  15. Z

    [moved] read and write the same address in SRAM

    Hi, Erikl, If DPS has no such prevention mechanism, is it common to write code by ourselves to detect the conflict and stop the write operation, only allow the read, because the write can be controlled by 'write_en' signal, while read doesn't have this kind of control.
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