zhangljz
Member level 5
Hi,
I am using encounter for PR, and I tried a very simple design but found unconstrained path. the netlist for PR is :
Only one flip-flop
the constrain file is
after I import the design, when I check" report_timing -unconstrained "
I got 3 unconstrained points, including the clk, and rstb. even the path between clk port and flip-flop clock pin are unconstrained. I am confused.
Anybody knows how to fix this ?
Thank you
I am using encounter for PR, and I tried a very simple design but found unconstrained path. the netlist for PR is :
Only one flip-flop
the constrain file is
after I import the design, when I check" report_timing -unconstrained "
I got 3 unconstrained points, including the clk, and rstb. even the path between clk port and flip-flop clock pin are unconstrained. I am confused.
Anybody knows how to fix this ?
Thank you