clock gating cell bound in SOC encounter

[zhangljz]

Hi,

I am using encounter for PR, and in the design there are many clock gating cells that are implemented with " LATCH+ AND" gates.

After PR, I found that the LATCH and AND gates are separated far away, like 100um. Is there any way in encounter to restrict the distance between them?

Thank you

 

[morris_mano]

usually the technology library come with the standard cell for clock gating. You can use that so that you don't have to worry about placement of latch and AND.

 

[zhangljz]

Hi morris_mano,

The technology is very old, and there is no ICG cell in the library, so I have to use individual latch + and .