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HI, we have solved this issue recently.
Maybe you can refer to the following way:
the problem is caused by mismatch between DEF and RTL. To be more specific, there are wrong hierarchy paths of macro in DEF. However, the tool will still floorplan it but the real one declared in RTL will also be...
Re: DC -topo Error
I have a same issue right now. But this flow works well before.
Now I'm just wondering if it's caused by the version of ICC. I'm not sure.
But it's not the size of die area.
It's better for you to prepare two timing constraints ( common part and specific part ) for each scenarios.
After that, MCMM ( Multi-corner multi-mode ) is one of the way for your purpose.
But for PrimeTime, you can analyze each timing respectively. One for 2:1 mode and the other for 1:1 mode.
If your STA signoff is promising, maybe the error is caused by the asynchronous path if there are multiple scan clock.
The other reason maybe the relationship between active edge of clock and probe point for measurement.
It's better to check your simulated waveform for more details.
If...
Maybe you should be care of that how the area is calculated by APR tool.
Generally speaking, the area reported by APR tool is chip area instead of cell area.
Therefore, "utilization" / "layout of macro" / "wire connection" may affect the chip area.
Very interesting idea!
I have never though this before.
To verify the correctness, the way of "old netlist v.s. new netlist" can be applied.
By the way, I think that it's seldom to occur due to the following reason:
1. the RTL file is developed by the company itself or must be licensed by...
You have to consider "the length of clock tree"
In the other words, the hold time violation will occur for the flip-flops with same clock source if the clock tree are not balanced.
Also, same clock frequency with different phase may cause this problem too.
Therefore, you have to do timing...
maybe the following current formula of transistor explain this:
this is the formula when MOSFET try to operate in linear mode and move to saturation.
for lower threshold voltage, the induced driving current increase faster than those with higher vt.
I think that it's the reason why the low...
HI, eeStud,
You have to know that you need extra physical library for topographical mode.
This physical library includes milkyway library and floorplanning information defined by IC compiler.
In the other words, you can't directly apply topographical mode without assistance of back-end info...
Did you set the following commands first before optimization ?
set_tlu_plus_files
set_mw_lib_reference
open_mw_lib
This is like set_target_library and you need to specify where the physical library is.
The application means that
1. how much is the length of your packet
2. what is the protocol you want to design for
Generally, the (2) is the most important factor when you decide polynomial for CRC.
Once the protocol is specified, the length of packet and polynomial for CRC are also decided...
Awesome of you!
Very thankful of you, I have never heard these two words before.
Originally I just want to check out why post-sim is inconsistent with RTL simulation even though signoff pass.
With your help, it indicates that there can be unnecessary bugs in RTL.
I have searched for the key...
The low power technique you means is power-gating.
It is the technique that you can turn off the power supply for specific region within IC.
Here the "turn off" means no power supply instead of inactive state.
For example, you would like to turn off the power supply of arithmetic during sleep...
I agree with you.
I have referred to specification of Verilog 1995 and 2001.
Both of them states that either of operand is unknown, the result will be unknown.
However, the result is not consistent when executing with NC-Verilog.
Maybe we can try this on different simulators.
HI~!
I'd like to make sure one thing and listen what you have thought.
What would happened if unknown is shown in equality operand during RTL simulation ?
for example, what happened to r if a, b, c become unknown in following description ?
always @ ( posedge clk or posedge rst )
if ( rst...
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