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Recent content by youyang

  1. Y

    TSMC 130um inductor with width of 30um

    What kind of issues should I consider if I want to use 30um width inductor? Area is not a problem. Through ADS Momentum, the self-oscillation frequency is also not a problem for expected band. The Q factor of 30um width is larger than that of 15um or 9um. What else? Why it seems people like use...
  2. Y

    Has anyone even run TSMC130 RF PDK DRC rule files (version 2.3) in Assura3.2

    Thanks guys, I finally install av4.1 and it works for the rule.
  3. Y

    Has anyone even run TSMC130 RF PDK DRC rule files (version 2.3) in Assura3.2

    Acctually, this rule file version is qualified by Assura4.1 and I do encounter some errors when using Assura3.2. These errors indicate something wrong in rule file, which should be error free. The question is right now only assura3.2 is availiable to me. I am not sure whether I have to move to...
  4. Y

    Has anyone even run TSMC130 RF PDK DRC rule files (version 2.3) in Assura3.2

    Has anyone ever run TSMC130 RF PDK DRC rule files (version 2.3) in Assura3.2 Is there any problem? BTW,can I use Assura4.1 in IC5141?
  5. Y

    Can I use Assura4.1 in IC5141?

    Can I use Assura4.1 in IC5141? Has anyone even run TSMC130 RF PDK DRC rule files (version 2.3) in Assura3.2? Really appreciated.
  6. Y

    Issue in PSS simulation

    Hi All, When I run the VCO PSS simulation, the spectre gave me the attached log file, saying the frequency is divided by 2 at a node. The node here is a terminal of DC biasing resistor, nothing special and there is no divide-by-2 block. The nominal frequency should be twice of the 6GHz, which...
  7. Y

    Help, who use TSMC 65nm Stardard cell?

    Hi JP, Thanks a lot. It's good enough for my use.
  8. Y

    Help, who use TSMC 65nm Stardard cell?

    Hi JP, I can only access RF PDK, which doesn't include Standard Cell stuffs. More accurately, I want to know the dff performance of GP and 1V (or 1.2V) power supply. Can you help me? I want to know the Clk to Q time, Setup and Hold.
  9. Y

    Help, who use TSMC 65nm Stardard cell?

    Hi all, Is there anyone can access TSMC 65nm stardard cell datasheet? I am wondering whether its DFF (static? or dynamic?) can be functional up to 1.6GHz. Any reply is appreciated.
  10. Y

    How to verify SigmaDelta desgin in Synthesizer

    Hi All, I have a MASH111 digital SDM coding in verilog. I am now confused about how to verify whether the SDM design is right or not. I mean the input (both integer and fraction parts) has so many possible patterns that I can't verify its function exhausively. Does someone have methodology on...
  11. Y

    Help about Spectre AMS simulation

    Hi, I am trying a trasistor-level inverter using Spectre AMS, but it shot me with following error message. I believe that I have the correct analog model path. Does anyone have idea about this error? ____________________________________________________________________ ncelab: 05.60-s006: (c)...
  12. Y

    Help about Current mirror designed use subthreshold mos

    Hi, Have anybody read the paper "MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design", in which the auther links the 'mismatch' with 'gm/Id' rather than just device's operation area.? He finds that for a given Id, the mismatch improved with a increasing...
  13. Y

    Help about Current mirror designed use subthreshold mos

    Hi DenisMark, Among Vinput,Voutput,mismatch,and output impedance, I agree with you that anti-mismatch and anti-noise should be the big problemes in this design. BTW, Thanks for your reference attached.
  14. Y

    Help about Current mirror designed use subthreshold mos

    Hi all, What should be taken into account in designing a current mirror using subthreshold pmos, where Vds > 5*VT(26mv)? Since the Vgs's control on Ids is much more stronger in subthreshold area than in saturate area, the current copy performance of current mirror using subthreshold pmos is...
  15. Y

    Why does PMOS beyond 130nm has positive Ion/Temp curve?

    Hi dick_freebird, Yes, that is what we have seen, but why?.. why is temperature pushing (V-VT)**2 up, more than channel mobility down? BTW, the 130nm PMOS in question has a high |VT|, around 1V, because of low leakage.
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