Why does PMOS beyond 130nm has positive Ion/Temp curve?

[youyang]

Hi all,

In my mind, for NMOS and PMOS, the Ion is decreasing with temperature, but in a 130nm process, through spice simulation, I found the 1.8V PMOS has another picture that Ion increases with temperature. Some other technologies beyond 130ns also have the same situation that the worst(slow) PVT corner of standardcell lib reaches at SS/low voltage/low temp instead of tranditionally SS/low voltage/high temp.

Could anybody explain this in terms of semiconductor process for me?
Any reply would be appreciated!

 

[dick_freebird]

If temperature is pushing (V-VT)**2 up, more than channel
mobility down, your square-law device physics may produce
a net gain.

Low voltage, short-channel technologies have tended
to reduce |VT| targets as well as geometry.

 

[youyang]

Hi dick_freebird,

Yes, that is what we have seen, but why?.. why is temperature pushing (V-VT)**2 up, more than channel mobility down?

BTW, the 130nm PMOS in question has a high |VT|, around 1V, because of low leakage.

If temperature is pushing (V-VT)**2 up, more than channel
mobility down, your square-law device physics may produce
a net gain.

Low voltage, short-channel technologies have tended
to reduce |VT| targets as well as geometry.