Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
That's what I understood too. however, when I increased the magnitude, then gain became bigger. that doesn' t make sense, isn't it supposed to be reduced because vin is inversely proportional to gain????
cadence ac magnitude
I was wondering why AC magnitude is 1 V when simulating circuits in cadence.
why not 2, 3 or 4??
Thanks for answering my question ahead
The llink doesn not exit
h**p://www.mit.edu/~ddaly/projects/775_OpAmp.pdf
I would very much appreciate if you could upload the link or file.
Best Regards
If the spec of my fully differential opamp contains slew rate is 20 v/usec, does that mean the slew rate in my design has to be greater or less than the value?
For example, does slew rate 300 v/usec in my design satisfy the spec?
Thanks ahead.
Another question, I need to build a CMFB to have...
I found the link from weal-weal posting but the link was removed.
h**p://www.mit.edu/~ddaly/projects/775_OpAmp.pdf
I really need the source does anybody has the source?
or I would very appreciate if you can let me know any pdf or papers i can prefer.
I am designing fully folded cascode OTA with PMOS input and CMFB. Whenever I run Cadence, the simulation result is way different from my hand calculation result and I am having hard time to make my OTA work on operating point and I really don't know what to do..
I would very much appreciate if...
When we design op-amp, the first thing you need to do is the decision of length of transistors in your design. How do you determine the reasonable length?
For example, TSMC 0.18 micron Technology.. should the length be greater than 0.18um??? or does that depend on each topollogy??
I am...
0.18 micron technology vdsat
I am trying to decide effective voltages for each transistors in the figure.
In normal folded cascode, its output swing is derived by Vout=2( vdd-(vov1+vov3+vov5+vov7)).. which I am actualy unsure.
wil there be any change in the output swing calculation if I...
vds vgs
Vds, Vgs, Vdsat of PMOS are negative. If I convert it into positive, do I have to subtract them from 1.8V( PMOS2V) or can I just use the absolute number of them?
I am trying to estimate Lambda and UCox of TSMC0.18 by hand calculation.
I do not know what "effbeta"from the equation above and how to find the value.
Also How do we find "ron" for the second equation?
Added after 4 minutes:
Added after 9 minutes:
On the first one, NMOS is connected to 1st stage while PMOS is connected to 1st stage in the second one. How does the change effect to this circuits?
Added after 4 minutes:
On the first one, NMOS is connected to 1st stage while PMOS is connected to 1st stage in the second one. How does the change effect to this circuits?
Hey yschuang,
I looked at the paper and found the topollogy. However, the second stage does not include the current tail transistor which my figure includes.
Does that change anything?
Added after 4 minutes:
Can you explain what the difference between the circuit above and this one
Can anyone explain how the second stage of this topollogy works? The first stage looks like a telescopic op amp but I am not sure about that as well. I have never seen this type of topollogy. I would also appreciate if you can let me know any text book covers this topology.
With much appreciation
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.