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It is usually dependent on how much current will be running through your s/d contact. You will have to take into account electromigration rules, plus series resistance effects across the channel of your transistor. For example, if you have a very long device which is running a lot of current, you will get different vgs bias points across the length of the channel due to the series resistance.
On the other hand, if you are running at low current and your concern is low-noise, then you size it so that your series gate resistance decreases to the value you require.
Theoretically, there's no limit
Reality, there IS.
From sim. model, there's a limit because all process engineers won't characterize all sizes for you. They usually characterize up to say 20um as length and 100um as width. Unless you specify the "m" factor in netlist, you won't be able to simulate further.
In reality, too large a device tends to have very large process variation unless you give to do that, like in large current output amplifier which tends to be over 10000um as width or some DC-DC converter, regulator.
On the other hand, there's a min. length and width.
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