Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yln2k2

  1. Y

    How to verify a netlist generated by synthesis tool.

    gatelevel simulation Hi , Please take care of following ... 1) Libraries - zero delay simulation models ... 2) For synthesis netlist you can skip "specify" blocks ... so check what option to skip the same ... for vcs/modelsim option is +nospecify 3) Top Level HDL need to replaced with netlist...
  2. Y

    embedding compiled code into Verilog RTL code of EEPROM

    Hi , when you code EPROM behavioral code you can use a memory array . regards yln
  3. Y

    How to design the circuit of clock multiplication?

    Hi , You could you xor gates to do the same provided you should have shifted version of I/P clk ? This ckt going to be pure combinational . one I/P of XOR is direct clk other I/P is T/4 shifted version of clk . in this way you can generate multiply by two clk . This is almost 50% duty cycle...
  4. Y

    Why should we have non-blocking statements in an always block?

    Re: Always Block Pretty good explanation by previous reply . Just I want to add one more point . synthesis results are what design intent but simulator understands in a diff way so there is a possibility getting diff results from simulation and netlist ... Thanks & Regards yln
  5. Y

    clock domain crossing question

    Hi , 1) Control signal to be stable or active more than one clk period of slow clk 2) Data should be stable until control signal is properly latched ( you can use Ack singnal from slow clk domain) 3)Above method may slow down your throughput better use Async FIFO if you need continuous data T/F...
  6. Y

    Which is more closer to real time scenario "negedge clk" or "posedge clk" testbench?

    Re: Test Bench Hi , Use same posedge clk with 1ns delay on signals you are driving and take signals after 1ns delay . with this delay u should not see any issue if so then there is a prob with RTL . Thanks & Regards yln
  7. Y

    Physical Compiler v/s Astro

    Hi , I am more like a Front end guy .. please correct me if i am wrong ... P.C : is logic optimization tool based on placement where as DC don't have placement information . PC take floor plan (either from jupitor or any other floor plan engine) .... P.C algorithms are different than which...
  8. Y

    Question about coverage in VCS NTB environment

    urg vcs Hi , you can specify coverage directory using following switch ... use this switch with simv ... Once you get different coverage files you can merge the same using cm_View ... Thanks & Regards yln -cm_dir <directory_path_name> Specifies and alternative name and location for the...
  9. Y

    Hierarchical signal referencing in VHDL

    what is modelsim_lib Hi , From the error message i can say either one of the signal defination is missing . >verror <erro_number> is saying vsim Message # 3569: The specified object could not be found in the design. Use the structure, signals, and variables windows to verify the existence...
  10. Y

    Formality RTL vs. netlist

    Hi , I am not sure . But if you have some floating I/P when you instantiated a module , DC by default drive 0 . Please make sure you don't have any floating I/P . Thanks & Regards yln
  11. Y

    What is the difference between clock buffer and normal buffer?

    Re: buffer problem Just to add one more , the diff delay should be min for all PVT corners ... regards yln
  12. Y

    Hierarchical signal referencing in VHDL

    init_signal_spy vhdl Hi , could you please post exact error message . 1) which simulator u r using ? looks like this procedure is avaliable in modelsim only ? 2) i assume u are using library modelsim_lib; use modelsim_lib.all for use these functions ? 3) address_spy should be in current...
  13. Y

    Looking for a company that can produce ASIC designs

    Re: ASIC design Hi , May I know the type of design u r looking ? may be you can send mail to yln2k@yahoo.com regards yln
  14. Y

    Interface Implementation

    Hi , Rule of thumb , no tristate in SOC ( it will consume more power) . use separate bus for read and write . you may need more cycles as you need to generate control signal for mux ... Thanks & Regards yln
  15. Y

    Hierarchical signal referencing in VHDL

    modelsim_lib Hi , When u spy a signal one of the parameter should be current hierarchy . looks like you gave both in dut hierarchy . I am attaching a pdf with example ... regards yln
See more

Part and Inventory Search

Back
Top