Hierarchical signal referencing in VHDL

[V]

init_signal_spy

I have to access a signal which is say in DUT_1. Now this DUT_1 is instantiated in DUT_2, DUT_2 in DUT_3 and DUT_3 in DUT_4.

Now in test bench i m called top level DUT_4, How can i access that signal which is there in DUT_1 in my VHDL test bench.

Note for that i have used signal spy but getting error........

init_signal_driver ("/testbench/DUT_4/DUT_3/DUT_2/DIT_1/SOURCE_SIGNAL", "/testbench/DUT_4/DUT_3/DUT_2/DIT_1/DESTN_SIGNAL_spy" );

But it is not working...what to do??? in VHDL......

thanks!!!!!!!!

 

[megastar007]

init_signal_driver

Can you tell me the reason why you want to access spy signal from tb.

 

[yln2k2]

modelsim_lib

Hi ,

When u spy a signal one of the parameter should be current hierarchy . looks like you gave both in dut hierarchy .

I am attaching a pdf with example ...


regards
yln

 

[V]

$init_signal_spy

hello year in 2002

thanks 4 that pdf.....i have it already..

now see this is the thing...what i am doing..

what i have.....
siganl address(7:0) is there in entity called DUT.
now that DUT is instantiated in DUT1, DUT1 is instantiated in DUT2
and finally in my testbench called design_tb im calling DUT2.

what i want.....
i want to access address signal from DUT in my testbench called design_tb..
I am using VHDL......

init_signal_spy ("/design_tb/DUT2/DUT1/DUT/address", "/design_tb/DUT2/address_spy" );
.........................................................................................................


Thnaks..

 

[yln2k2]

init_signal_spy vhdl

Hi ,

could you please post exact error message .
1) which simulator u r using ? looks like this procedure is avaliable in modelsim only ?
2) i assume u are using library modelsim_lib; use modelsim_lib.all for use these functions ?
3) address_spy should be in current hierarchy ? then you can use directly /address_spy .

I am pasting example from modelsim manual ....
library ieee, modelsim_lib;
use ieee.std_logic_1164.all
use modelsim_lib.util.all;
entity top is
end;

architecture only of top is
signal top_sig1 : std_logic;
begin
...
spy_process : process
begin
init_signal_spy("/top/uut/inst1/sig1","/top_sig1",1);
wait;
end process spy_process;
...

 

[V]

signal spy vhdl

Hi
--***********FORMAT TO USE SIGNAL SPY*******************------

--init_signal_driver ("/testbench name/DUT instantiation_1/DUT instantiation_2/...../DUT instantiation_N/source signal", "/destination signal" ); ----------Is it correct????????

OR

--init_signal_driver ("/testbench name/Entity name_1/Entity name_2/...../Last entity/DUT instantiation_N in last entity/source signal", "/testbench name/DUT instantiation/destination signal" ); --------------------Is it correct????????

OR something else.....i have tried many options..



what i am doing......
process
begin

init_signal_spy ("/design_tb/DUT_2/DUT_1/DUT/address", "/wr_addr_spy" );

--- how i am interpreting above line init_signal_spy("/ testbench name/instantiation name_1 in test bench/instantiation name_2/final signal","/destination signal in --testbench" );

wait;
end process;


# ** Error: (vsim-3569) init_signal_spy [C:/vhdl file location/design_tb.vhd] : Object '/design_tb/DUT_2/address_spy' does not exist in the design.


Any idea where i m wrong??

 

[yln2k2]

what is modelsim_lib

Hi ,

From the error message i can say either one of the signal defination is missing .
>verror <erro_number> is saying

vsim Message # 3569:
The specified object could not be found in the design. Use the
structure, signals, and variables windows to verify the existence of
and the hierarchical name of the object.

could you please check whether hierarchy is fine ? if so i didn't see any other issue ..


Thanks & Regards
yln

 

[littlefrog]

Good morning,

I have a question for you:

if I have a level with a generate module, for example:


A_Rx_Controller_array_generation:
FOR i IN 9 DOWNTO 0 GENERATE
Comp_A_Rx_Controller:
A_Rx_Controller PORT MAP(
Rst => RST,
Clk => Per_Clk,
RxP => RxP(i),
RxM => RxM(i),
);
END GENERATE;


And there are 10 level for this signal

|Top|APeripheral:Comp_APeripheral|A_Rx_Controller:\A_Rx_Controller_array_generation:0:Comp_A_Rx_Controller

|Top|APeripheral:Comp_APeripheral|A_Rx_Controller:\A_Rx_Controller_array_generation:1:Comp_A_Rx_Controller

|Top|APeripheral:Comp_APeripheral|A_Rx_Controller:\A_Rx_Controller_array_generation:2:Comp_A_Rx_Controller

.....


what is the statement of signal force for this example???


Thanks