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Recent content by yellff

  1. yellff

    Question on the ESD protection failed test

    Re: ESD help some expert has told me ,ESD current just like flood rush into a city, and you just find if there are huge trench let them go. I think GNDA to VDDD have the same diode with the Digital I/O ,just like two same trench,maybe have two direction,maybe choose the VDDD can damage the...
  2. yellff

    What is the overload recovery of comparator?

    overload recovery comparator Is it mean large signal input ?
  3. yellff

    Are you always tidy up your circuit in artist(cadence ic5)?

    How can you deal with your circuit to a beautiful art circuit?what is your standard?
  4. yellff

    The difference between sections in Laker tech file ?

    Re: Laker Tech file ? I had use laker,Ialso wanto know
  5. yellff

    Are your company's analog team includes the ESD designer ?

    Are your company's analog team includes the ESD designer ?In my company ,we must do ESD circuit and layout.
  6. yellff

    Low Voltage(1.2v) CMOS bandgap design

    This is 0.13um's refence .than how about 90nm?
  7. yellff

    Papers on temperature sensors in mainstream CMOS

    Re: Temperature sensor! I remember a sensor can be implemented by differential cap and resistor .
  8. yellff

    The difference between recursive and transversal filter

    IS recursive filter IIR,and transersal filter FIR especially with taps?
  9. yellff

    Who have the e-book of "Analysis and Design of Pipeline

    Re: Who have the e-book of "Analysis and Design of Pipe Thanks,I find this book,but the bookstores have not. Added after 1 minutes: I search this book,can someone can copy to me.
  10. yellff

    How we use the MOS capacitance as varactor?

    I layout a p-varactor and a n-varactor,how much different are they in the capacitance change rate with the gate voltage?
  11. yellff

    Analog and Digital Design

    I think digital's future is software,with software 's thought ,and software's tools, make digital product.But analog 's future sure enter into common place,It will not be not very mystery ,and grasped by many company ,and many engineer.
  12. yellff

    Problem with 2-stage flash ADC layout

    Re: ADC Layout problem I think the LSB comparator's layout ,and the reference is very crtical.
  13. yellff

    How can we generate a dither in A/D modulator?

    Why we say the dither will be ineffective if it is quantized down to just 1 bit.And the dither performs resonably well with only three levels,but as may as eight quantization levels may be needed to asympotically approach the quality of effectiveness of unquantized dither.

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