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I try this:
assert rising_edge(clk_osc_C) and clk_osc_C'last_event >= 10 ns
report "the width of clk_osc_C is too narrow"
severity ERROR;
bu failed, can any body give me some suggestion?
How to force the DC to generate TIEHI and TIELO
Hi All, I'm working on a project and I encountered a problem. After systhesis, I check the gate-netlist and found that: some ports of sub-block are assign to be 1'b0, 1'b1. But in normal condition, it should be connected to TIEHI and TIELO block...
Hi poluekt, thank you for your replay ,I had used the command: report_constaint -all_violators
and got such message:
the design has no violated constraints
no. so I add sdf information, it's right now.
Thank you.
But I still wonder, why? I mean, the sdf just increase the net delay. whit out this, the timing performance should be better.
bow
Hi All, I designed a counter ,and set clock constraint as follow:
create_clock -period 8 -waveform {0 4} [get_ports clk]
do compile and get the synthesised file for simulation.
the timing report as follow([all_registers])
Point Incr Path...
In one block, all registers are all driven by "clk", but some registers(Type A) are control by "clk_en" by Enable pin.
Some is there any dc command to find all the (type A) registers?
bow
I thought it should be like this:
module xyz();
reg [31:0] addrmem [31:0]
initial begin
for ( i=0 ; i<32 ; i++)
begin
addrmem[i] = $random();
end
end
endmodule
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